Integrated Shared Memory
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81
rtl/shared_memory/VX_shared_memory_block.v
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81
rtl/shared_memory/VX_shared_memory_block.v
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module VX_shared_memory_block (
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input clk, // Clock
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input wire[6:0] addr,
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input wire[3:0][31:0] wdata,
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input wire[1:0] we,
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input wire shm_write,
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output wire[3:0][31:0] data_out
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);
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logic [3:0][31:0] shared_memory[127:0];
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//wire need_to_write = (|we);
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always @(posedge clk) begin
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if(shm_write) begin
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if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
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if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
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if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
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if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
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end
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end
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assign data_out = shm_write ? 0 : shared_memory[addr];
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// wire cena = 1;
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// wire cenb = shm_write;
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// wire[3:0][31:0] write_bit_mask;
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// assign write_bit_mask[0] = (we == 2'b00) ? 0 : {32{1'b1}};
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// assign write_bit_mask[1] = (we == 2'b01) ? 0 : {32{1'b1}};
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// assign write_bit_mask[2] = (we == 2'b10) ? 0 : {32{1'b1}};
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// assign write_bit_mask[3] = (we == 2'b11) ? 0 : {32{1'b1}};
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// // Using ASIC MEM
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// /* verilator lint_off PINCONNECTEMPTY */
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// rf2_128x128_wm1 first_ram (
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// .CENYA(),
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// .AYA(),
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// .CENYB(),
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// .WENYB(),
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// .AYB(),
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// .QA(data_out),
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// .SOA(),
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// .SOB(),
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// .CLKA(clk),
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// .CENA(cena),
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// .AA(addr),
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// .CLKB(clk),
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// .CENB(cenb),
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// .WENB(write_bit_mask),
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// .AB(addr),
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// .DB(wdata),
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// .EMAA(3'b011),
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// .EMASA(1'b0),
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// .EMAB(3'b011),
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// .TENA(1'b1),
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// .TCENA(1'b0),
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// .TAA(5'b0),
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// .TENB(1'b1),
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// .TCENB(1'b0),
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// .TWENB(128'b0),
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// .TAB(5'b0),
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// .TDB(128'b0),
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// .RET1N(1'b1),
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// .SIA(2'b0),
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// .SEA(1'b0),
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// .DFTRAMBYP(1'b0),
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// .SIB(2'b0),
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// .SEB(1'b0),
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// .COLLDISN(1'b1)
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// );
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// /* verilator lint_on PINCONNECTEMPTY */
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endmodule
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