From b748a7665d61e5b43fed2e156f1ccf2698fc59e2 Mon Sep 17 00:00:00 2001 From: "Lyons, Ethan Tyler" Date: Thu, 21 Nov 2019 21:41:41 -0500 Subject: [PATCH] Synthesis Compatible --- rtl/cache/VX_d_cache.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/rtl/cache/VX_d_cache.v b/rtl/cache/VX_d_cache.v index fd6c9641..78b407f7 100644 --- a/rtl/cache/VX_d_cache.v +++ b/rtl/cache/VX_d_cache.v @@ -304,9 +304,15 @@ module VX_d_cache // 0; wire[1:0] byte_select = bank_addr[1:0]; + wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START]; + + `ifdef SYN_FUNC + wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = 0; + wire[IND_SIZE_END:IND_SIZE_START] cache_index = 0; + `else wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START]; wire[IND_SIZE_END:IND_SIZE_START] cache_index = bank_addr[ADDR_IND_END:ADDR_IND_START]; - wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START]; + `endif wire normal_valid_in = valid_per_bank[bank_id];