diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v index a55145af..cfbd02d7 100644 --- a/rtl/cache/VX_cache_data.v +++ b/rtl/cache/VX_cache_data.v @@ -171,9 +171,13 @@ module VX_cache_data + // Try to fix the error in memory conneciton, modified by Lingjun Zhu on Oct. 28 2019 + // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid}; + // wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m; - wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid}; - wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m; + wire[19-1:0] wdata_m = {new_tag, new_dirty, new_valid}; + + wire[19-1:0] data_out_m; assign {old_tag, old_dirty, old_valid} = data_out_m; @@ -210,7 +214,7 @@ module VX_cache_data .TCENB(1'b0), // .TWENB(128'b0), .TAB(8'b0), - .TDB(128'b0), + .TDB(19'b0), .RET1N(1'b1), .SIA(2'b0), .SEA(1'b0), diff --git a/syn/dc.log b/syn/dc.log index 340079ad..ac85e8ff 100644 --- a/syn/dc.log +++ b/syn/dc.log @@ -647,14 +647,6 @@ Presto compilation completed successfully. Information: Building the design 'VX_cache_data' instantiated from design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8' with the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_WORDS_PER_BLOCK=4". (HDL-193) Presto compilation completed successfully. -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) 1 link @@ -669,23 +661,7 @@ link USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb (library) /tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (LINK-5) -0 +1 set clk_freq 100 100 set clk_period [expr 1000.0 / $clk_freq / 1.0] @@ -720,7 +696,7 @@ Information: Evaluating DesignWare library utilization. (UISN-27) Information: Sequential output inversion is enabled. SVF file must be used for formal verification. (OPT-1208) -Information: There are 9060 potential problems in your design. Please run 'check_design' for more information. (LINT-99) +Information: There are 8963 potential problems in your design. Please run 'check_design' for more information. (LINT-99) Information: Uniquified 4 instances of design 'VX_alu'. (OPT-1056) Information: Uniquified 9 instances of design 'VX_generic_priority_encoder_N4'. (OPT-1056) @@ -734,24 +710,540309 @@ Information: Uniquified 8 instances of design 'VX_gpr_I_VX_gpr_read_VX_gpr_read_ Information: Uniquified 8 instances of design 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (OPT-1056) Simplifying Design 'Vortex' -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_7'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_7'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_6'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_6'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_5'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_5'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_4'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_4'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_3'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_3'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_2'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_2'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_1'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_1'. (LINK-5) -Error: Width mismatch on port 'QA' of reference to 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_0'. (LINK-3) -Warning: Unable to resolve reference 'rf2_256x19_wm0' in 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_0'. (LINK-5) Loaded alib file './alib-52/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db.alib' Information: State dependent leakage is now switched from on to off. Beginning Pass 1 Mapping ------------------------ + Processing 'VX_shared_memory_NB7_BITS_PER_BANK3' + Processing 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' + Processing 'VX_warp_scheduler' +Information: Added key list 'DesignWare' to design 'VX_warp_scheduler'. (DDB-72) + Implement Synthetic for 'VX_warp_scheduler'. + Processing 'Vortex' + Processing 'VX_generic_register_N487' + Processing 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' + Processing 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' + Implement Synthetic for 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__'. + Processing 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter___0' + Processing 'VX_writeback_I_VX_mem_wb_VX_inst_mem_wb_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_csr_wb_VX_csr_wb_inter__I_VX_writeback_inter_VX_wb_inter__' + Processing 'VX_fetch_I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__I_icache_response_VX_icache_response_inter__I_icache_request_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_fe_inst_meta_fd_VX_inst_meta_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' + Processing 'VX_alu_0' + Implement Synthetic for 'VX_alu_0'. + Processing 'VX_alu_0_DW_div_uns_J8_0' + Processing 'VX_alu_0_DW_div_tc_J8_0' + Processing 'VX_alu_0_DW01_absval_J8_0' + Processing 'VX_alu_0_DW01_inc_J8_0' + Processing 'VX_alu_0_DW_div_uns_J8_1' + Processing 'VX_alu_0_DW_div_tc_J8_1' + Processing 'VX_alu_0_DW01_absval_J8_1' + Processing 'VX_alu_0_DW01_inc_J8_1' +Information: Added key list 'DesignWare' to design 'VX_alu_0'. (DDB-72) + Processing 'VX_generic_register_N71' + Processing 'VX_bank_valids_NB7_BITS_PER_BANK3' + Processing 'VX_generic_register_N308' + Processing 'VX_lsu_addr_gen' + Implement Synthetic for 'VX_lsu_addr_gen'. + Processing 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' +Information: Added key list 'DesignWare' to design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3'. (DDB-72) + Processing 'VX_priority_encoder_w_mask_N4_0' +Information: Added key list 'DesignWare' to design 'VX_priority_encoder_w_mask_N4_0'. (DDB-72) + Processing 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' + Processing 'VX_shared_memory_block_0' + Processing 'VX_priority_encoder' + Processing 'VX_generic_priority_encoder_N4_8' + Processing 'VX_generic_register_N203' + Processing 'VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__' + Processing 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' + Processing 'VX_countones_N4_0' +Information: Added key list 'DesignWare' to design 'VX_countones_N4_0'. (DDB-72) + Processing 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' + Processing 'VX_cache_bank_valid_NUMBER_BANKS8' + Processing 'VX_generic_stack_WIDTH37_DEPTH2_0' +Information: Added key list 'DesignWare' to design 'VX_generic_stack_WIDTH37_DEPTH2_0'. (DDB-72) + Processing 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' + Processing 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' +Information: Added key list 'DesignWare' to design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. (DDB-72) + Implement Synthetic for 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. + Processing 'VX_inst_multiplex_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_gpr_data_VX_gpr_data_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' + Processing 'VX_generic_priority_encoder_N4_0' + Processing 'VX_generic_register_N240' + Processing 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_0' + Processing 'VX_generic_priority_encoder_N8' + Processing 'VX_csr_wrapper_I_VX_csr_req_VX_csr_req_inter__I_VX_csr_wb_VX_csr_wb_inter__' + Processing 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' + Processing 'VX_lsu_I_VX_lsu_req_VX_lsu_req_inter__I_VX_mem_wb_VX_inst_mem_wb_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' + Processing 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_0' +Information: Added key list 'DesignWare' to design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_0'. (DDB-72) + Processing 'VX_decode_I_fd_inst_meta_de_VX_inst_meta_inter__I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__' +Information: Added key list 'DesignWare' to design 'VX_decode_I_fd_inst_meta_de_VX_inst_meta_inter__I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__'. (DDB-72) + Implement Synthetic for 'VX_decode_I_fd_inst_meta_de_VX_inst_meta_inter__I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__'. + Processing 'VX_generic_register_N60' + Processing 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' + Processing 'VX_countones_N8_0' + Implement Synthetic for 'VX_countones_N8_0'. +Information: Added key list 'DesignWare' to design 'VX_countones_N8_0'. (DDB-72) + + Updating timing information +Information: Updating design information... (UID-85) +Information: The library cell 'TIELO_X1M_A12TUL_C35' in the library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c' is not characterized for internal power. (PWR-536) +Information: The library cell 'TIEHI_X1M_A12TUL_C35' in the library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c' is not characterized for internal power. (PWR-536) +Information: The target library(s) contains cell(s), other than black boxes, that are not characterized for internal power. (PWR-24) + + Beginning Mapping Optimizations (Ultra High effort) + ------------------------------- +Information: Added key list 'DesignWare' to design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__'. (DDB-72) + Structuring 'VX_alu_3_DW_div_uns_0' + Mapping 'VX_alu_3_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_0' + Mapping 'VX_alu_3_DW01_add_1' + Mapping 'VX_alu_3_DW01_add_2' + Mapping 'VX_alu_3_DW01_add_3' + Mapping 'VX_alu_3_DW01_add_4' + Mapping 'VX_alu_3_DW01_add_5' + Mapping 'VX_alu_3_DW01_add_6' + Mapping 'VX_alu_3_DW01_add_7' + Mapping 'VX_alu_3_DW01_add_8' + Mapping 'VX_alu_3_DW01_add_9' + Mapping 'VX_alu_3_DW01_add_10' + Mapping 'VX_alu_3_DW01_add_11' + Mapping 'VX_alu_3_DW01_add_12' + Mapping 'VX_alu_3_DW01_add_13' + Mapping 'VX_alu_3_DW01_add_14' + Mapping 'VX_alu_3_DW01_add_15' + Mapping 'VX_alu_3_DW01_add_16' + Mapping 'VX_alu_3_DW01_add_17' + Mapping 'VX_alu_3_DW01_add_18' + Mapping 'VX_alu_3_DW01_add_19' + Mapping 'VX_alu_3_DW01_add_20' + Mapping 'VX_alu_3_DW01_add_21' + Mapping 'VX_alu_3_DW01_add_22' + Mapping 'VX_alu_3_DW01_add_23' + Mapping 'VX_alu_3_DW01_add_24' + Mapping 'VX_alu_3_DW01_add_25' + Mapping 'VX_alu_3_DW01_add_26' + Structuring 'VX_alu_3_DW_div_uns_1' + Mapping 'VX_alu_3_DW_div_uns_1' + Mapping 'VX_alu_3_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_28' + Mapping 'VX_alu_3_DW01_add_29' + Mapping 'VX_alu_3_DW01_add_30' + Mapping 'VX_alu_3_DW01_add_31' + Mapping 'VX_alu_3_DW01_add_32' + Mapping 'VX_alu_3_DW01_add_33' + Mapping 'VX_alu_3_DW01_add_34' + Mapping 'VX_alu_3_DW01_add_35' + Mapping 'VX_alu_3_DW01_add_36' + Mapping 'VX_alu_3_DW01_add_37' + Mapping 'VX_alu_3_DW01_add_38' + Mapping 'VX_alu_3_DW01_add_39' + Mapping 'VX_alu_3_DW01_add_40' + Mapping 'VX_alu_3_DW01_add_41' + Mapping 'VX_alu_3_DW01_add_42' + Mapping 'VX_alu_3_DW01_add_43' + Mapping 'VX_alu_3_DW01_add_44' + Mapping 'VX_alu_3_DW01_add_45' + Mapping 'VX_alu_3_DW01_add_46' + Mapping 'VX_alu_3_DW01_add_47' + Mapping 'VX_alu_3_DW01_add_48' + Mapping 'VX_alu_3_DW01_add_49' + Mapping 'VX_alu_3_DW01_add_50' + Mapping 'VX_alu_3_DW01_add_51' + Mapping 'VX_alu_3_DW01_add_52' + Mapping 'VX_alu_3_DW01_add_53' + Mapping 'VX_alu_3_DW01_add_54' + Mapping 'VX_alu_3_DW01_add_55' + Mapping 'VX_alu_3_DW01_add_56' + Mapping 'VX_alu_3_DW01_add_57' + Mapping 'VX_alu_3_DW01_add_58' + Mapping 'VX_alu_3_DW01_add_59' + Mapping 'VX_alu_3_DW01_add_60' + Mapping 'VX_alu_3_DW01_add_61' + Mapping 'VX_alu_3_DW01_add_62' + Mapping 'VX_alu_3_DW01_add_63' + Mapping 'VX_alu_3_DW01_add_64' + Mapping 'VX_alu_3_DW01_add_65' + Mapping 'VX_alu_3_DW01_add_66' + Structuring 'VX_alu_3_DW_div_uns_2' + Mapping 'VX_alu_3_DW_div_uns_2' + Mapping 'VX_alu_3_DW01_add_67' + Mapping 'VX_alu_3_DW01_add_68' + Mapping 'VX_alu_3_DW01_add_69' + Mapping 'VX_alu_3_DW01_sub_0' + Mapping 'VX_alu_3_DW01_add_70' + Mapping 'VX_alu_3_DW01_add_71' + Mapping 'VX_alu_3_DW01_add_72' + Mapping 'VX_alu_3_DW01_add_77' + Mapping 'VX_alu_3_DW01_add_78' + Mapping 'VX_alu_3_DW01_add_79' + Mapping 'VX_alu_3_DW01_add_80' + Mapping 'VX_alu_3_DW01_add_81' + Mapping 'VX_alu_3_DW01_add_82' + Mapping 'VX_alu_3_DW01_add_83' + Mapping 'VX_alu_3_DW01_add_84' + Mapping 'VX_alu_3_DW01_add_85' + Mapping 'VX_alu_3_DW01_add_86' + Mapping 'VX_alu_3_DW01_add_87' + Mapping 'VX_alu_3_DW01_add_88' + Mapping 'VX_alu_3_DW01_add_89' + Mapping 'VX_alu_3_DW01_add_90' + Mapping 'VX_alu_3_DW01_add_91' + Mapping 'VX_alu_3_DW01_add_92' + Mapping 'VX_alu_3_DW01_add_93' + Mapping 'VX_alu_3_DW01_add_94' + Mapping 'VX_alu_3_DW01_add_95' + Mapping 'VX_alu_3_DW01_add_96' + Mapping 'VX_alu_3_DW01_add_97' + Mapping 'VX_alu_3_DW01_add_98' + Mapping 'VX_alu_3_DW01_add_99' + Mapping 'VX_alu_3_DW01_add_100' + Mapping 'VX_alu_3_DW01_add_101' + Mapping 'VX_alu_3_DW01_add_102' + Mapping 'VX_alu_3_DW01_add_103' + Mapping 'VX_alu_3_DW01_add_104' + Mapping 'VX_alu_3_DW01_add_105' + Mapping 'VX_alu_3_DW01_add_106' + Mapping 'VX_alu_3_DW01_add_107' + Mapping 'VX_alu_3_DW01_add_108' + Mapping 'VX_alu_3_DW01_add_109' + Mapping 'VX_alu_3_DW01_add_110' + Mapping 'VX_alu_3_DW01_add_111' + Mapping 'VX_alu_3_DW01_add_112' + Mapping 'VX_alu_3_DW01_add_113' + Mapping 'VX_alu_3_DW01_add_114' + Mapping 'VX_alu_3_DW01_add_115' + Mapping 'VX_alu_3_DW01_add_116' + Mapping 'VX_alu_3_DW01_add_117' + Mapping 'VX_alu_3_DW01_add_118' + Mapping 'VX_alu_3_DW01_add_119' + Mapping 'VX_alu_3_DW01_add_120' + Mapping 'VX_alu_3_DW01_add_121' + Mapping 'VX_alu_3_DW01_add_122' + Mapping 'VX_alu_3_DW01_add_123' + Mapping 'VX_alu_3_DW01_add_124' + Mapping 'VX_alu_3_DW01_add_125' + Mapping 'VX_alu_3_DW01_add_126' + Mapping 'VX_alu_3_DW01_add_127' + Mapping 'VX_alu_3_DW01_add_128' + Mapping 'VX_alu_3_DW01_add_129' + Mapping 'VX_alu_3_DW01_add_130' + Mapping 'VX_alu_3_DW01_add_131' + Mapping 'VX_alu_3_DW01_add_132' + Mapping 'VX_alu_3_DW01_add_133' + Mapping 'VX_alu_3_DW01_add_134' + Mapping 'VX_alu_3_DW01_add_135' + Mapping 'VX_alu_3_DW01_add_136' + Mapping 'VX_alu_3_DW01_add_137' + Mapping 'VX_alu_3_DW01_add_138' + Mapping 'VX_alu_3_DW01_add_139' + Mapping 'VX_alu_3_DW01_add_140' + Mapping 'VX_alu_3_DW01_add_141' + Mapping 'VX_alu_3_DW01_add_142' + Mapping 'VX_alu_3_DW01_add_143' + Mapping 'VX_alu_3_DW01_add_144' + Mapping 'VX_alu_3_DW01_add_145' + Mapping 'VX_alu_3_DW01_add_146' + Structuring 'VX_alu_3_DW_div_tc_0' + Mapping 'VX_alu_3_DW_div_tc_0' + Structuring 'VX_alu_3_DW01_absval_0' + Mapping 'VX_alu_3_DW01_absval_0' + Structuring 'VX_alu_3_DW01_inc_0' + Mapping 'VX_alu_3_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_147' + Mapping 'VX_alu_3_DW01_add_148' + Mapping 'VX_alu_3_DW01_add_149' + Mapping 'VX_alu_3_DW01_add_150' + Mapping 'VX_alu_3_DW01_add_151' + Mapping 'VX_alu_3_DW01_add_152' + Mapping 'VX_alu_3_DW01_add_153' + Mapping 'VX_alu_3_DW01_add_154' + Mapping 'VX_alu_3_DW01_add_155' + Mapping 'VX_alu_3_DW01_add_156' + Mapping 'VX_alu_3_DW01_add_157' + Mapping 'VX_alu_3_DW01_add_158' + Mapping 'VX_alu_3_DW01_add_159' + Mapping 'VX_alu_3_DW01_add_160' + Mapping 'VX_alu_3_DW01_add_161' + Mapping 'VX_alu_3_DW01_add_162' + Mapping 'VX_alu_3_DW01_add_163' + Mapping 'VX_alu_3_DW01_add_164' + Mapping 'VX_alu_3_DW01_add_165' + Mapping 'VX_alu_3_DW01_add_166' + Mapping 'VX_alu_3_DW01_add_167' + Mapping 'VX_alu_3_DW01_add_168' + Mapping 'VX_alu_3_DW01_add_169' + Mapping 'VX_alu_3_DW01_add_170' + Mapping 'VX_alu_3_DW01_add_171' + Mapping 'VX_alu_3_DW01_add_172' + Mapping 'VX_alu_3_DW01_add_173' + Mapping 'VX_alu_3_DW_inc_1' + Structuring 'VX_alu_3_DW_div_tc_1' + Mapping 'VX_alu_3_DW_div_tc_1' + Structuring 'VX_alu_3_DW01_absval_1' + Mapping 'VX_alu_3_DW01_absval_1' + Structuring 'VX_alu_3_DW01_inc_1' + Mapping 'VX_alu_3_DW01_inc_1' + Mapping 'VX_alu_3_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_175' + Mapping 'VX_alu_3_DW01_add_176' + Mapping 'VX_alu_3_DW01_add_177' + Mapping 'VX_alu_3_DW01_add_178' + Mapping 'VX_alu_3_DW01_add_179' + Mapping 'VX_alu_3_DW01_add_180' + Mapping 'VX_alu_3_DW01_add_181' + Mapping 'VX_alu_3_DW01_add_182' + Mapping 'VX_alu_3_DW01_add_183' + Mapping 'VX_alu_3_DW01_add_184' + Mapping 'VX_alu_3_DW01_add_185' + Mapping 'VX_alu_3_DW01_add_186' + Mapping 'VX_alu_3_DW01_add_187' + Mapping 'VX_alu_3_DW01_add_188' + Mapping 'VX_alu_3_DW01_add_189' + Mapping 'VX_alu_3_DW01_add_190' + Mapping 'VX_alu_3_DW01_add_191' + Mapping 'VX_alu_3_DW01_add_192' + Mapping 'VX_alu_3_DW01_add_193' + Mapping 'VX_alu_3_DW01_add_194' + Mapping 'VX_alu_3_DW01_add_195' + Mapping 'VX_alu_3_DW01_add_196' + Mapping 'VX_alu_3_DW01_add_197' + Mapping 'VX_alu_3_DW01_add_198' + Mapping 'VX_alu_3_DW01_add_199' + Mapping 'VX_alu_3_DW01_add_200' + Mapping 'VX_alu_3_DW01_add_201' + Mapping 'VX_alu_3_DW01_add_202' + Mapping 'VX_alu_3_DW01_add_203' + Mapping 'VX_alu_3_DW01_add_204' + Mapping 'VX_alu_3_DW01_add_205' + Mapping 'VX_alu_3_DW01_add_206' + Mapping 'VX_alu_3_DW01_add_207' + Mapping 'VX_alu_3_DW01_add_208' + Mapping 'VX_alu_3_DW01_add_209' + Mapping 'VX_alu_3_DW01_add_210' + Mapping 'VX_alu_3_DW01_add_211' + Mapping 'VX_alu_3_DW01_add_212' + Mapping 'VX_alu_3_DW01_add_213' + Mapping 'VX_alu_3_DW_inc_3' + Structuring 'VX_alu_3_DW_div_tc_2' + Mapping 'VX_alu_3_DW_div_tc_2' + Structuring 'VX_alu_3_DW01_absval_2' + Mapping 'VX_alu_3_DW01_absval_2' + Structuring 'VX_alu_3_DW01_inc_2' + Mapping 'VX_alu_3_DW01_inc_2' + Mapping 'VX_alu_3_DW01_add_214' + Mapping 'VX_alu_3_DW01_add_215' + Mapping 'VX_alu_3_DW01_add_216' + Mapping 'VX_alu_3_DW01_sub_1' + Mapping 'VX_alu_3_DW01_add_217' + Mapping 'VX_alu_3_DW01_add_218' + Mapping 'VX_alu_3_DW01_add_219' + Mapping 'VX_alu_3_DW01_add_224' + Mapping 'VX_alu_3_DW01_add_225' + Mapping 'VX_alu_3_DW01_add_226' + Mapping 'VX_alu_3_DW01_add_227' + Mapping 'VX_alu_3_DW01_add_228' + Mapping 'VX_alu_3_DW01_add_229' + Mapping 'VX_alu_3_DW01_add_230' + Mapping 'VX_alu_3_DW01_add_231' + Mapping 'VX_alu_3_DW01_add_232' + Mapping 'VX_alu_3_DW01_add_233' + Mapping 'VX_alu_3_DW01_add_234' + Mapping 'VX_alu_3_DW01_add_235' + Mapping 'VX_alu_3_DW01_add_236' + Mapping 'VX_alu_3_DW01_add_237' + Mapping 'VX_alu_3_DW01_add_238' + Mapping 'VX_alu_3_DW01_add_239' + Mapping 'VX_alu_3_DW01_add_240' + Mapping 'VX_alu_3_DW01_add_241' + Mapping 'VX_alu_3_DW01_add_242' + Mapping 'VX_alu_3_DW01_add_243' + Mapping 'VX_alu_3_DW01_add_244' + Mapping 'VX_alu_3_DW01_add_245' + Mapping 'VX_alu_3_DW01_add_246' + Mapping 'VX_alu_3_DW01_add_247' + Mapping 'VX_alu_3_DW01_add_248' + Mapping 'VX_alu_3_DW01_add_249' + Mapping 'VX_alu_3_DW01_add_250' + Mapping 'VX_alu_3_DW01_add_251' + Mapping 'VX_alu_3_DW01_add_252' + Mapping 'VX_alu_3_DW01_add_253' + Mapping 'VX_alu_3_DW01_add_254' + Mapping 'VX_alu_3_DW01_add_255' + Mapping 'VX_alu_3_DW01_add_256' + Mapping 'VX_alu_3_DW01_add_257' + Mapping 'VX_alu_3_DW01_add_258' + Mapping 'VX_alu_3_DW01_add_259' + Mapping 'VX_alu_3_DW01_add_260' + Mapping 'VX_alu_3_DW01_add_261' + Mapping 'VX_alu_3_DW01_add_262' + Mapping 'VX_alu_3_DW01_add_263' + Mapping 'VX_alu_3_DW01_add_264' + Mapping 'VX_alu_3_DW01_add_265' + Mapping 'VX_alu_3_DW01_add_266' + Mapping 'VX_alu_3_DW01_add_267' + Mapping 'VX_alu_3_DW01_add_268' + Mapping 'VX_alu_3_DW01_add_269' + Mapping 'VX_alu_3_DW01_add_270' + Mapping 'VX_alu_3_DW01_add_271' + Mapping 'VX_alu_3_DW01_add_272' + Mapping 'VX_alu_3_DW01_add_273' + Mapping 'VX_alu_3_DW01_add_274' + Mapping 'VX_alu_3_DW01_add_275' + Mapping 'VX_alu_3_DW01_add_276' + Mapping 'VX_alu_3_DW01_add_277' + Mapping 'VX_alu_3_DW01_add_278' + Mapping 'VX_alu_3_DW01_add_279' + Mapping 'VX_alu_3_DW01_add_280' + Mapping 'VX_alu_3_DW01_add_281' + Mapping 'VX_alu_3_DW01_add_282' + Mapping 'VX_alu_3_DW01_add_283' + Mapping 'VX_alu_3_DW01_add_284' + Mapping 'VX_alu_3_DW01_add_285' + Mapping 'VX_alu_3_DW01_add_286' + Mapping 'VX_alu_3_DW01_add_287' + Mapping 'VX_alu_3_DW01_add_288' + Mapping 'VX_alu_3_DW01_add_289' + Mapping 'VX_alu_3_DW01_add_290' + Mapping 'VX_alu_3_DW01_add_291' + Mapping 'VX_alu_3_DW01_add_292' + Mapping 'VX_alu_3_DW01_add_293' + Mapping 'VX_alu_3_DW_inc_5' + Structuring 'VX_alu_3_DW_div_uns_3' + Mapping 'VX_alu_3_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_294' + Mapping 'VX_alu_3_DW01_add_295' + Mapping 'VX_alu_3_DW01_add_296' + Mapping 'VX_alu_3_DW01_add_297' + Mapping 'VX_alu_3_DW01_add_298' + Mapping 'VX_alu_3_DW01_add_299' + Mapping 'VX_alu_3_DW01_add_300' + Mapping 'VX_alu_3_DW01_add_301' + Mapping 'VX_alu_3_DW01_add_302' + Mapping 'VX_alu_3_DW01_add_303' + Mapping 'VX_alu_3_DW01_add_304' + Mapping 'VX_alu_3_DW01_add_305' + Mapping 'VX_alu_3_DW01_add_306' + Mapping 'VX_alu_3_DW01_add_307' + Mapping 'VX_alu_3_DW01_add_308' + Mapping 'VX_alu_3_DW01_add_309' + Mapping 'VX_alu_3_DW01_add_310' + Mapping 'VX_alu_3_DW01_add_311' + Mapping 'VX_alu_3_DW01_add_312' + Mapping 'VX_alu_3_DW01_add_313' + Mapping 'VX_alu_3_DW01_add_314' + Mapping 'VX_alu_3_DW01_add_315' + Mapping 'VX_alu_3_DW01_add_316' + Mapping 'VX_alu_3_DW01_add_317' + Mapping 'VX_alu_3_DW01_add_318' + Mapping 'VX_alu_3_DW01_add_319' + Mapping 'VX_alu_3_DW01_add_320' + Structuring 'VX_alu_3_DW_div_uns_4' + Mapping 'VX_alu_3_DW_div_uns_4' + Mapping 'VX_alu_3_DW01_add_321' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_322' + Mapping 'VX_alu_3_DW01_add_323' + Mapping 'VX_alu_3_DW01_add_324' + Mapping 'VX_alu_3_DW01_add_325' + Mapping 'VX_alu_3_DW01_add_326' + Mapping 'VX_alu_3_DW01_add_327' + Mapping 'VX_alu_3_DW01_add_328' + Mapping 'VX_alu_3_DW01_add_329' + Mapping 'VX_alu_3_DW01_add_330' + Mapping 'VX_alu_3_DW01_add_331' + Mapping 'VX_alu_3_DW01_add_332' + Mapping 'VX_alu_3_DW01_add_333' + Mapping 'VX_alu_3_DW01_add_334' + Mapping 'VX_alu_3_DW01_add_335' + Mapping 'VX_alu_3_DW01_add_336' + Mapping 'VX_alu_3_DW01_add_337' + Mapping 'VX_alu_3_DW01_add_338' + Mapping 'VX_alu_3_DW01_add_339' + Mapping 'VX_alu_3_DW01_add_340' + Mapping 'VX_alu_3_DW01_add_341' + Mapping 'VX_alu_3_DW01_add_342' + Mapping 'VX_alu_3_DW01_add_343' + Mapping 'VX_alu_3_DW01_add_344' + Mapping 'VX_alu_3_DW01_add_345' + Mapping 'VX_alu_3_DW01_add_346' + Mapping 'VX_alu_3_DW01_add_347' + Mapping 'VX_alu_3_DW01_add_348' + Mapping 'VX_alu_3_DW01_add_349' + Mapping 'VX_alu_3_DW01_add_350' + Mapping 'VX_alu_3_DW01_add_351' + Mapping 'VX_alu_3_DW01_add_352' + Mapping 'VX_alu_3_DW01_add_353' + Mapping 'VX_alu_3_DW01_add_354' + Mapping 'VX_alu_3_DW01_add_355' + Mapping 'VX_alu_3_DW01_add_356' + Mapping 'VX_alu_3_DW01_add_357' + Mapping 'VX_alu_3_DW01_add_358' + Mapping 'VX_alu_3_DW01_add_359' + Mapping 'VX_alu_3_DW01_add_360' + Structuring 'VX_alu_3_DW_div_uns_5' + Mapping 'VX_alu_3_DW_div_uns_5' + Mapping 'VX_alu_3_DW01_add_361' + Mapping 'VX_alu_3_DW01_add_362' + Mapping 'VX_alu_3_DW01_add_363' + Mapping 'VX_alu_3_DW01_sub_2' + Mapping 'VX_alu_3_DW01_add_364' + Mapping 'VX_alu_3_DW01_add_365' + Mapping 'VX_alu_3_DW01_add_366' + Mapping 'VX_alu_3_DW01_add_371' + Mapping 'VX_alu_3_DW01_add_372' + Mapping 'VX_alu_3_DW01_add_373' + Mapping 'VX_alu_3_DW01_add_374' + Mapping 'VX_alu_3_DW01_add_375' + Mapping 'VX_alu_3_DW01_add_376' + Mapping 'VX_alu_3_DW01_add_377' + Mapping 'VX_alu_3_DW01_add_378' + Mapping 'VX_alu_3_DW01_add_379' + Mapping 'VX_alu_3_DW01_add_380' + Mapping 'VX_alu_3_DW01_add_381' + Mapping 'VX_alu_3_DW01_add_382' + Mapping 'VX_alu_3_DW01_add_383' + Mapping 'VX_alu_3_DW01_add_384' + Mapping 'VX_alu_3_DW01_add_385' + Mapping 'VX_alu_3_DW01_add_386' + Mapping 'VX_alu_3_DW01_add_387' + Mapping 'VX_alu_3_DW01_add_388' + Mapping 'VX_alu_3_DW01_add_389' + Mapping 'VX_alu_3_DW01_add_390' + Mapping 'VX_alu_3_DW01_add_391' + Mapping 'VX_alu_3_DW01_add_392' + Mapping 'VX_alu_3_DW01_add_393' + Mapping 'VX_alu_3_DW01_add_394' + Mapping 'VX_alu_3_DW01_add_395' + Mapping 'VX_alu_3_DW01_add_396' + Mapping 'VX_alu_3_DW01_add_397' + Mapping 'VX_alu_3_DW01_add_398' + Mapping 'VX_alu_3_DW01_add_399' + Mapping 'VX_alu_3_DW01_add_400' + Mapping 'VX_alu_3_DW01_add_401' + Mapping 'VX_alu_3_DW01_add_402' + Mapping 'VX_alu_3_DW01_add_403' + Mapping 'VX_alu_3_DW01_add_404' + Mapping 'VX_alu_3_DW01_add_405' + Mapping 'VX_alu_3_DW01_add_406' + Mapping 'VX_alu_3_DW01_add_407' + Mapping 'VX_alu_3_DW01_add_408' + Mapping 'VX_alu_3_DW01_add_409' + Mapping 'VX_alu_3_DW01_add_410' + Mapping 'VX_alu_3_DW01_add_411' + Mapping 'VX_alu_3_DW01_add_412' + Mapping 'VX_alu_3_DW01_add_413' + Mapping 'VX_alu_3_DW01_add_414' + Mapping 'VX_alu_3_DW01_add_415' + Mapping 'VX_alu_3_DW01_add_416' + Mapping 'VX_alu_3_DW01_add_417' + Mapping 'VX_alu_3_DW01_add_418' + Mapping 'VX_alu_3_DW01_add_419' + Mapping 'VX_alu_3_DW01_add_420' + Mapping 'VX_alu_3_DW01_add_421' + Mapping 'VX_alu_3_DW01_add_422' + Mapping 'VX_alu_3_DW01_add_423' + Mapping 'VX_alu_3_DW01_add_424' + Mapping 'VX_alu_3_DW01_add_425' + Mapping 'VX_alu_3_DW01_add_426' + Mapping 'VX_alu_3_DW01_add_427' + Mapping 'VX_alu_3_DW01_add_428' + Mapping 'VX_alu_3_DW01_add_429' + Mapping 'VX_alu_3_DW01_add_430' + Mapping 'VX_alu_3_DW01_add_431' + Mapping 'VX_alu_3_DW01_add_432' + Mapping 'VX_alu_3_DW01_add_433' + Mapping 'VX_alu_3_DW01_add_434' + Mapping 'VX_alu_3_DW01_add_435' + Mapping 'VX_alu_3_DW01_add_436' + Mapping 'VX_alu_3_DW01_add_437' + Mapping 'VX_alu_3_DW01_add_438' + Mapping 'VX_alu_3_DW01_add_439' + Mapping 'VX_alu_3_DW01_add_440' + Structuring 'VX_alu_3_DW_div_tc_3' + Mapping 'VX_alu_3_DW_div_tc_3' + Structuring 'VX_alu_3_DW01_absval_3' + Mapping 'VX_alu_3_DW01_absval_3' + Structuring 'VX_alu_3_DW01_inc_3' + Mapping 'VX_alu_3_DW01_inc_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_441' + Mapping 'VX_alu_3_DW01_add_442' + Mapping 'VX_alu_3_DW01_add_443' + Mapping 'VX_alu_3_DW01_add_444' + Mapping 'VX_alu_3_DW01_add_445' + Mapping 'VX_alu_3_DW01_add_446' + Mapping 'VX_alu_3_DW01_add_447' + Mapping 'VX_alu_3_DW01_add_448' + Mapping 'VX_alu_3_DW01_add_449' + Mapping 'VX_alu_3_DW01_add_450' + Mapping 'VX_alu_3_DW01_add_451' + Mapping 'VX_alu_3_DW01_add_452' + Mapping 'VX_alu_3_DW01_add_453' + Mapping 'VX_alu_3_DW01_add_454' + Mapping 'VX_alu_3_DW01_add_455' + Mapping 'VX_alu_3_DW01_add_456' + Mapping 'VX_alu_3_DW01_add_457' + Mapping 'VX_alu_3_DW01_add_458' + Mapping 'VX_alu_3_DW01_add_459' + Mapping 'VX_alu_3_DW01_add_460' + Mapping 'VX_alu_3_DW01_add_461' + Mapping 'VX_alu_3_DW01_add_462' + Mapping 'VX_alu_3_DW01_add_463' + Mapping 'VX_alu_3_DW01_add_464' + Mapping 'VX_alu_3_DW01_add_465' + Mapping 'VX_alu_3_DW01_add_466' + Mapping 'VX_alu_3_DW01_add_467' + Mapping 'VX_alu_3_DW_inc_6' + Structuring 'VX_alu_3_DW_div_tc_4' + Mapping 'VX_alu_3_DW_div_tc_4' + Structuring 'VX_alu_3_DW01_absval_4' + Mapping 'VX_alu_3_DW01_absval_4' + Structuring 'VX_alu_3_DW01_inc_4' + Mapping 'VX_alu_3_DW01_inc_4' + Mapping 'VX_alu_3_DW01_add_468' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_469' + Mapping 'VX_alu_3_DW01_add_470' + Mapping 'VX_alu_3_DW01_add_471' + Mapping 'VX_alu_3_DW01_add_472' + Mapping 'VX_alu_3_DW01_add_473' + Mapping 'VX_alu_3_DW01_add_474' + Mapping 'VX_alu_3_DW01_add_475' + Mapping 'VX_alu_3_DW01_add_476' + Mapping 'VX_alu_3_DW01_add_477' + Mapping 'VX_alu_3_DW01_add_478' + Mapping 'VX_alu_3_DW01_add_479' + Mapping 'VX_alu_3_DW01_add_480' + Mapping 'VX_alu_3_DW01_add_481' + Mapping 'VX_alu_3_DW01_add_482' + Mapping 'VX_alu_3_DW01_add_483' + Mapping 'VX_alu_3_DW01_add_484' + Mapping 'VX_alu_3_DW01_add_485' + Mapping 'VX_alu_3_DW01_add_486' + Mapping 'VX_alu_3_DW01_add_487' + Mapping 'VX_alu_3_DW01_add_488' + Mapping 'VX_alu_3_DW01_add_489' + Mapping 'VX_alu_3_DW01_add_490' + Mapping 'VX_alu_3_DW01_add_491' + Mapping 'VX_alu_3_DW01_add_492' + Mapping 'VX_alu_3_DW01_add_493' + Mapping 'VX_alu_3_DW01_add_494' + Mapping 'VX_alu_3_DW01_add_495' + Mapping 'VX_alu_3_DW01_add_496' + Mapping 'VX_alu_3_DW01_add_497' + Mapping 'VX_alu_3_DW01_add_498' + Mapping 'VX_alu_3_DW01_add_499' + Mapping 'VX_alu_3_DW01_add_500' + Mapping 'VX_alu_3_DW01_add_501' + Mapping 'VX_alu_3_DW01_add_502' + Mapping 'VX_alu_3_DW01_add_503' + Mapping 'VX_alu_3_DW01_add_504' + Mapping 'VX_alu_3_DW01_add_505' + Mapping 'VX_alu_3_DW01_add_506' + Mapping 'VX_alu_3_DW01_add_507' + Mapping 'VX_alu_3_DW_inc_8' + Structuring 'VX_alu_3_DW_div_tc_5' + Mapping 'VX_alu_3_DW_div_tc_5' + Structuring 'VX_alu_3_DW01_absval_5' + Mapping 'VX_alu_3_DW01_absval_5' + Structuring 'VX_alu_3_DW01_inc_5' + Mapping 'VX_alu_3_DW01_inc_5' + Mapping 'VX_alu_3_DW01_add_508' + Mapping 'VX_alu_3_DW01_add_509' + Mapping 'VX_alu_3_DW01_add_510' + Mapping 'VX_alu_3_DW01_sub_3' + Mapping 'VX_alu_3_DW01_add_511' + Mapping 'VX_alu_3_DW01_add_512' + Mapping 'VX_alu_3_DW01_add_513' + Mapping 'VX_alu_3_DW01_add_518' + Mapping 'VX_alu_3_DW01_add_519' + Mapping 'VX_alu_3_DW01_add_520' + Mapping 'VX_alu_3_DW01_add_521' + Mapping 'VX_alu_3_DW01_add_522' + Mapping 'VX_alu_3_DW01_add_523' + Mapping 'VX_alu_3_DW01_add_524' + Mapping 'VX_alu_3_DW01_add_525' + Mapping 'VX_alu_3_DW01_add_526' + Mapping 'VX_alu_3_DW01_add_527' + Mapping 'VX_alu_3_DW01_add_528' + Mapping 'VX_alu_3_DW01_add_529' + Mapping 'VX_alu_3_DW01_add_530' + Mapping 'VX_alu_3_DW01_add_531' + Mapping 'VX_alu_3_DW01_add_532' + Mapping 'VX_alu_3_DW01_add_533' + Mapping 'VX_alu_3_DW01_add_534' + Mapping 'VX_alu_3_DW01_add_535' + Mapping 'VX_alu_3_DW01_add_536' + Mapping 'VX_alu_3_DW01_add_537' + Mapping 'VX_alu_3_DW01_add_538' + Mapping 'VX_alu_3_DW01_add_539' + Mapping 'VX_alu_3_DW01_add_540' + Mapping 'VX_alu_3_DW01_add_541' + Mapping 'VX_alu_3_DW01_add_542' + Mapping 'VX_alu_3_DW01_add_543' + Mapping 'VX_alu_3_DW01_add_544' + Mapping 'VX_alu_3_DW01_add_545' + Mapping 'VX_alu_3_DW01_add_546' + Mapping 'VX_alu_3_DW01_add_547' + Mapping 'VX_alu_3_DW01_add_548' + Mapping 'VX_alu_3_DW01_add_549' + Mapping 'VX_alu_3_DW01_add_550' + Mapping 'VX_alu_3_DW01_add_551' + Mapping 'VX_alu_3_DW01_add_552' + Mapping 'VX_alu_3_DW01_add_553' + Mapping 'VX_alu_3_DW01_add_554' + Mapping 'VX_alu_3_DW01_add_555' + Mapping 'VX_alu_3_DW01_add_556' + Mapping 'VX_alu_3_DW01_add_557' + Mapping 'VX_alu_3_DW01_add_558' + Mapping 'VX_alu_3_DW01_add_559' + Mapping 'VX_alu_3_DW01_add_560' + Mapping 'VX_alu_3_DW01_add_561' + Mapping 'VX_alu_3_DW01_add_562' + Mapping 'VX_alu_3_DW01_add_563' + Mapping 'VX_alu_3_DW01_add_564' + Mapping 'VX_alu_3_DW01_add_565' + Mapping 'VX_alu_3_DW01_add_566' + Mapping 'VX_alu_3_DW01_add_567' + Mapping 'VX_alu_3_DW01_add_568' + Mapping 'VX_alu_3_DW01_add_569' + Mapping 'VX_alu_3_DW01_add_570' + Mapping 'VX_alu_3_DW01_add_571' + Mapping 'VX_alu_3_DW01_add_572' + Mapping 'VX_alu_3_DW01_add_573' + Mapping 'VX_alu_3_DW01_add_574' + Mapping 'VX_alu_3_DW01_add_575' + Mapping 'VX_alu_3_DW01_add_576' + Mapping 'VX_alu_3_DW01_add_577' + Mapping 'VX_alu_3_DW01_add_578' + Mapping 'VX_alu_3_DW01_add_579' + Mapping 'VX_alu_3_DW01_add_580' + Mapping 'VX_alu_3_DW01_add_581' + Mapping 'VX_alu_3_DW01_add_582' + Mapping 'VX_alu_3_DW01_add_583' + Mapping 'VX_alu_3_DW01_add_584' + Mapping 'VX_alu_3_DW01_add_585' + Mapping 'VX_alu_3_DW01_add_586' + Mapping 'VX_alu_3_DW01_add_587' + Mapping 'VX_alu_3_DW_inc_10' + Structuring 'VX_alu_0_DW_div_uns_0' + Mapping 'VX_alu_0_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_0' + Mapping 'VX_alu_0_DW01_add_1' + Mapping 'VX_alu_0_DW01_add_2' + Mapping 'VX_alu_0_DW01_add_3' + Mapping 'VX_alu_0_DW01_add_4' + Mapping 'VX_alu_0_DW01_add_5' + Mapping 'VX_alu_0_DW01_add_6' + Mapping 'VX_alu_0_DW01_add_7' + Mapping 'VX_alu_0_DW01_add_8' + Mapping 'VX_alu_0_DW01_add_9' + Mapping 'VX_alu_0_DW01_add_10' + Mapping 'VX_alu_0_DW01_add_11' + Mapping 'VX_alu_0_DW01_add_12' + Mapping 'VX_alu_0_DW01_add_13' + Mapping 'VX_alu_0_DW01_add_14' + Mapping 'VX_alu_0_DW01_add_15' + Mapping 'VX_alu_0_DW01_add_16' + Mapping 'VX_alu_0_DW01_add_17' + Mapping 'VX_alu_0_DW01_add_18' + Mapping 'VX_alu_0_DW01_add_19' + Mapping 'VX_alu_0_DW01_add_20' + Mapping 'VX_alu_0_DW01_add_21' + Mapping 'VX_alu_0_DW01_add_22' + Mapping 'VX_alu_0_DW01_add_23' + Mapping 'VX_alu_0_DW01_add_24' + Mapping 'VX_alu_0_DW01_add_25' + Mapping 'VX_alu_0_DW01_add_26' + Structuring 'VX_alu_0_DW_div_uns_1' + Mapping 'VX_alu_0_DW_div_uns_1' + Mapping 'VX_alu_0_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_28' + Mapping 'VX_alu_0_DW01_add_29' + Mapping 'VX_alu_0_DW01_add_30' + Mapping 'VX_alu_0_DW01_add_31' + Mapping 'VX_alu_0_DW01_add_32' + Mapping 'VX_alu_0_DW01_add_33' + Mapping 'VX_alu_0_DW01_add_34' + Mapping 'VX_alu_0_DW01_add_35' + Mapping 'VX_alu_0_DW01_add_36' + Mapping 'VX_alu_0_DW01_add_37' + Mapping 'VX_alu_0_DW01_add_38' + Mapping 'VX_alu_0_DW01_add_39' + Mapping 'VX_alu_0_DW01_add_40' + Mapping 'VX_alu_0_DW01_add_41' + Mapping 'VX_alu_0_DW01_add_42' + Mapping 'VX_alu_0_DW01_add_43' + Mapping 'VX_alu_0_DW01_add_44' + Mapping 'VX_alu_0_DW01_add_45' + Mapping 'VX_alu_0_DW01_add_46' + Mapping 'VX_alu_0_DW01_add_47' + Mapping 'VX_alu_0_DW01_add_48' + Mapping 'VX_alu_0_DW01_add_49' + Mapping 'VX_alu_0_DW01_add_50' + Mapping 'VX_alu_0_DW01_add_51' + Mapping 'VX_alu_0_DW01_add_52' + Mapping 'VX_alu_0_DW01_add_53' + Mapping 'VX_alu_0_DW01_add_54' + Mapping 'VX_alu_0_DW01_add_55' + Mapping 'VX_alu_0_DW01_add_56' + Mapping 'VX_alu_0_DW01_add_57' + Mapping 'VX_alu_0_DW01_add_58' + Mapping 'VX_alu_0_DW01_add_59' + Mapping 'VX_alu_0_DW01_add_60' + Mapping 'VX_alu_0_DW01_add_61' + Mapping 'VX_alu_0_DW01_add_62' + Mapping 'VX_alu_0_DW01_add_63' + Mapping 'VX_alu_0_DW01_add_64' + Mapping 'VX_alu_0_DW01_add_65' + Mapping 'VX_alu_0_DW01_add_66' + Structuring 'VX_alu_0_DW_div_uns_2' + Mapping 'VX_alu_0_DW_div_uns_2' + Mapping 'VX_alu_0_DW01_add_67' + Mapping 'VX_alu_0_DW01_add_68' + Mapping 'VX_alu_0_DW01_add_69' + Mapping 'VX_alu_0_DW01_sub_0' + Mapping 'VX_alu_0_DW01_add_70' + Mapping 'VX_alu_0_DW01_add_71' + Mapping 'VX_alu_0_DW01_add_72' + Mapping 'VX_alu_0_DW01_add_77' + Mapping 'VX_alu_0_DW01_add_78' + Mapping 'VX_alu_0_DW01_add_79' + Mapping 'VX_alu_0_DW01_add_80' + Mapping 'VX_alu_0_DW01_add_81' + Mapping 'VX_alu_0_DW01_add_82' + Mapping 'VX_alu_0_DW01_add_83' + Mapping 'VX_alu_0_DW01_add_84' + Mapping 'VX_alu_0_DW01_add_85' + Mapping 'VX_alu_0_DW01_add_86' + Mapping 'VX_alu_0_DW01_add_87' + Mapping 'VX_alu_0_DW01_add_88' + Mapping 'VX_alu_0_DW01_add_89' + Mapping 'VX_alu_0_DW01_add_90' + Mapping 'VX_alu_0_DW01_add_91' + Mapping 'VX_alu_0_DW01_add_92' + Mapping 'VX_alu_0_DW01_add_93' + Mapping 'VX_alu_0_DW01_add_94' + Mapping 'VX_alu_0_DW01_add_95' + Mapping 'VX_alu_0_DW01_add_96' + Mapping 'VX_alu_0_DW01_add_97' + Mapping 'VX_alu_0_DW01_add_98' + Mapping 'VX_alu_0_DW01_add_99' + Mapping 'VX_alu_0_DW01_add_100' + Mapping 'VX_alu_0_DW01_add_101' + Mapping 'VX_alu_0_DW01_add_102' + Mapping 'VX_alu_0_DW01_add_103' + Mapping 'VX_alu_0_DW01_add_104' + Mapping 'VX_alu_0_DW01_add_105' + Mapping 'VX_alu_0_DW01_add_106' + Mapping 'VX_alu_0_DW01_add_107' + Mapping 'VX_alu_0_DW01_add_108' + Mapping 'VX_alu_0_DW01_add_109' + Mapping 'VX_alu_0_DW01_add_110' + Mapping 'VX_alu_0_DW01_add_111' + Mapping 'VX_alu_0_DW01_add_112' + Mapping 'VX_alu_0_DW01_add_113' + Mapping 'VX_alu_0_DW01_add_114' + Mapping 'VX_alu_0_DW01_add_115' + Mapping 'VX_alu_0_DW01_add_116' + Mapping 'VX_alu_0_DW01_add_117' + Mapping 'VX_alu_0_DW01_add_118' + Mapping 'VX_alu_0_DW01_add_119' + Mapping 'VX_alu_0_DW01_add_120' + Mapping 'VX_alu_0_DW01_add_121' + Mapping 'VX_alu_0_DW01_add_122' + Mapping 'VX_alu_0_DW01_add_123' + Mapping 'VX_alu_0_DW01_add_124' + Mapping 'VX_alu_0_DW01_add_125' + Mapping 'VX_alu_0_DW01_add_126' + Mapping 'VX_alu_0_DW01_add_127' + Mapping 'VX_alu_0_DW01_add_128' + Mapping 'VX_alu_0_DW01_add_129' + Mapping 'VX_alu_0_DW01_add_130' + Mapping 'VX_alu_0_DW01_add_131' + Mapping 'VX_alu_0_DW01_add_132' + Mapping 'VX_alu_0_DW01_add_133' + Mapping 'VX_alu_0_DW01_add_134' + Mapping 'VX_alu_0_DW01_add_135' + Mapping 'VX_alu_0_DW01_add_136' + Mapping 'VX_alu_0_DW01_add_137' + Mapping 'VX_alu_0_DW01_add_138' + Mapping 'VX_alu_0_DW01_add_139' + Mapping 'VX_alu_0_DW01_add_140' + Mapping 'VX_alu_0_DW01_add_141' + Mapping 'VX_alu_0_DW01_add_142' + Mapping 'VX_alu_0_DW01_add_143' + Mapping 'VX_alu_0_DW01_add_144' + Mapping 'VX_alu_0_DW01_add_145' + Mapping 'VX_alu_0_DW01_add_146' + Structuring 'VX_alu_1_DW_div_uns_0' + Mapping 'VX_alu_1_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_0' + Mapping 'VX_alu_1_DW01_add_1' + Mapping 'VX_alu_1_DW01_add_2' + Mapping 'VX_alu_1_DW01_add_3' + Mapping 'VX_alu_1_DW01_add_4' + Mapping 'VX_alu_1_DW01_add_5' + Mapping 'VX_alu_1_DW01_add_6' + Mapping 'VX_alu_1_DW01_add_7' + Mapping 'VX_alu_1_DW01_add_8' + Mapping 'VX_alu_1_DW01_add_9' + Mapping 'VX_alu_1_DW01_add_10' + Mapping 'VX_alu_1_DW01_add_11' + Mapping 'VX_alu_1_DW01_add_12' + Mapping 'VX_alu_1_DW01_add_13' + Mapping 'VX_alu_1_DW01_add_14' + Mapping 'VX_alu_1_DW01_add_15' + Mapping 'VX_alu_1_DW01_add_16' + Mapping 'VX_alu_1_DW01_add_17' + Mapping 'VX_alu_1_DW01_add_18' + Mapping 'VX_alu_1_DW01_add_19' + Mapping 'VX_alu_1_DW01_add_20' + Mapping 'VX_alu_1_DW01_add_21' + Mapping 'VX_alu_1_DW01_add_22' + Mapping 'VX_alu_1_DW01_add_23' + Mapping 'VX_alu_1_DW01_add_24' + Mapping 'VX_alu_1_DW01_add_25' + Mapping 'VX_alu_1_DW01_add_26' + Structuring 'VX_alu_1_DW_div_uns_1' + Mapping 'VX_alu_1_DW_div_uns_1' + Mapping 'VX_alu_1_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_28' + Mapping 'VX_alu_1_DW01_add_29' + Mapping 'VX_alu_1_DW01_add_30' + Mapping 'VX_alu_1_DW01_add_31' + Mapping 'VX_alu_1_DW01_add_32' + Mapping 'VX_alu_1_DW01_add_33' + Mapping 'VX_alu_1_DW01_add_34' + Mapping 'VX_alu_1_DW01_add_35' + Mapping 'VX_alu_1_DW01_add_36' + Mapping 'VX_alu_1_DW01_add_37' + Mapping 'VX_alu_1_DW01_add_38' + Mapping 'VX_alu_1_DW01_add_39' + Mapping 'VX_alu_1_DW01_add_40' + Mapping 'VX_alu_1_DW01_add_41' + Mapping 'VX_alu_1_DW01_add_42' + Mapping 'VX_alu_1_DW01_add_43' + Mapping 'VX_alu_1_DW01_add_44' + Mapping 'VX_alu_1_DW01_add_45' + Mapping 'VX_alu_1_DW01_add_46' + Mapping 'VX_alu_1_DW01_add_47' + Mapping 'VX_alu_1_DW01_add_48' + Mapping 'VX_alu_1_DW01_add_49' + Mapping 'VX_alu_1_DW01_add_50' + Mapping 'VX_alu_1_DW01_add_51' + Mapping 'VX_alu_1_DW01_add_52' + Mapping 'VX_alu_1_DW01_add_53' + Mapping 'VX_alu_1_DW01_add_54' + Mapping 'VX_alu_1_DW01_add_55' + Mapping 'VX_alu_1_DW01_add_56' + Mapping 'VX_alu_1_DW01_add_57' + Mapping 'VX_alu_1_DW01_add_58' + Mapping 'VX_alu_1_DW01_add_59' + Mapping 'VX_alu_1_DW01_add_60' + Mapping 'VX_alu_1_DW01_add_61' + Mapping 'VX_alu_1_DW01_add_62' + Mapping 'VX_alu_1_DW01_add_63' + Mapping 'VX_alu_1_DW01_add_64' + Mapping 'VX_alu_1_DW01_add_65' + Mapping 'VX_alu_1_DW01_add_66' + Structuring 'VX_alu_1_DW_div_uns_2' + Mapping 'VX_alu_1_DW_div_uns_2' + Mapping 'VX_alu_1_DW01_add_67' + Mapping 'VX_alu_1_DW01_add_68' + Mapping 'VX_alu_1_DW01_add_69' + Mapping 'VX_alu_1_DW01_sub_0' + Mapping 'VX_alu_1_DW01_add_70' + Mapping 'VX_alu_1_DW01_add_71' + Mapping 'VX_alu_1_DW01_add_72' + Mapping 'VX_alu_1_DW01_add_77' + Mapping 'VX_alu_1_DW01_add_78' + Mapping 'VX_alu_1_DW01_add_79' + Mapping 'VX_alu_1_DW01_add_80' + Mapping 'VX_alu_1_DW01_add_81' + Mapping 'VX_alu_1_DW01_add_82' + Mapping 'VX_alu_1_DW01_add_83' + Mapping 'VX_alu_1_DW01_add_84' + Mapping 'VX_alu_1_DW01_add_85' + Mapping 'VX_alu_1_DW01_add_86' + Mapping 'VX_alu_1_DW01_add_87' + Mapping 'VX_alu_1_DW01_add_88' + Mapping 'VX_alu_1_DW01_add_89' + Mapping 'VX_alu_1_DW01_add_90' + Mapping 'VX_alu_1_DW01_add_91' + Mapping 'VX_alu_1_DW01_add_92' + Mapping 'VX_alu_1_DW01_add_93' + Mapping 'VX_alu_1_DW01_add_94' + Mapping 'VX_alu_1_DW01_add_95' + Mapping 'VX_alu_1_DW01_add_96' + Mapping 'VX_alu_1_DW01_add_97' + Mapping 'VX_alu_1_DW01_add_98' + Mapping 'VX_alu_1_DW01_add_99' + Mapping 'VX_alu_1_DW01_add_100' + Mapping 'VX_alu_1_DW01_add_101' + Mapping 'VX_alu_1_DW01_add_102' + Mapping 'VX_alu_1_DW01_add_103' + Mapping 'VX_alu_1_DW01_add_104' + Mapping 'VX_alu_1_DW01_add_105' + Mapping 'VX_alu_1_DW01_add_106' + Mapping 'VX_alu_1_DW01_add_107' + Mapping 'VX_alu_1_DW01_add_108' + Mapping 'VX_alu_1_DW01_add_109' + Mapping 'VX_alu_1_DW01_add_110' + Mapping 'VX_alu_1_DW01_add_111' + Mapping 'VX_alu_1_DW01_add_112' + Mapping 'VX_alu_1_DW01_add_113' + Mapping 'VX_alu_1_DW01_add_114' + Mapping 'VX_alu_1_DW01_add_115' + Mapping 'VX_alu_1_DW01_add_116' + Mapping 'VX_alu_1_DW01_add_117' + Mapping 'VX_alu_1_DW01_add_118' + Mapping 'VX_alu_1_DW01_add_119' + Mapping 'VX_alu_1_DW01_add_120' + Mapping 'VX_alu_1_DW01_add_121' + Mapping 'VX_alu_1_DW01_add_122' + Mapping 'VX_alu_1_DW01_add_123' + Mapping 'VX_alu_1_DW01_add_124' + Mapping 'VX_alu_1_DW01_add_125' + Mapping 'VX_alu_1_DW01_add_126' + Mapping 'VX_alu_1_DW01_add_127' + Mapping 'VX_alu_1_DW01_add_128' + Mapping 'VX_alu_1_DW01_add_129' + Mapping 'VX_alu_1_DW01_add_130' + Mapping 'VX_alu_1_DW01_add_131' + Mapping 'VX_alu_1_DW01_add_132' + Mapping 'VX_alu_1_DW01_add_133' + Mapping 'VX_alu_1_DW01_add_134' + Mapping 'VX_alu_1_DW01_add_135' + Mapping 'VX_alu_1_DW01_add_136' + Mapping 'VX_alu_1_DW01_add_137' + Mapping 'VX_alu_1_DW01_add_138' + Mapping 'VX_alu_1_DW01_add_139' + Mapping 'VX_alu_1_DW01_add_140' + Mapping 'VX_alu_1_DW01_add_141' + Mapping 'VX_alu_1_DW01_add_142' + Mapping 'VX_alu_1_DW01_add_143' + Mapping 'VX_alu_1_DW01_add_144' + Mapping 'VX_alu_1_DW01_add_145' + Mapping 'VX_alu_1_DW01_add_146' + Structuring 'VX_alu_2_DW_div_uns_0' + Mapping 'VX_alu_2_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_0' + Mapping 'VX_alu_2_DW01_add_1' + Mapping 'VX_alu_2_DW01_add_2' + Mapping 'VX_alu_2_DW01_add_3' + Mapping 'VX_alu_2_DW01_add_4' + Mapping 'VX_alu_2_DW01_add_5' + Mapping 'VX_alu_2_DW01_add_6' + Mapping 'VX_alu_2_DW01_add_7' + Mapping 'VX_alu_2_DW01_add_8' + Mapping 'VX_alu_2_DW01_add_9' + Mapping 'VX_alu_2_DW01_add_10' + Mapping 'VX_alu_2_DW01_add_11' + Mapping 'VX_alu_2_DW01_add_12' + Mapping 'VX_alu_2_DW01_add_13' + Mapping 'VX_alu_2_DW01_add_14' + Mapping 'VX_alu_2_DW01_add_15' + Mapping 'VX_alu_2_DW01_add_16' + Mapping 'VX_alu_2_DW01_add_17' + Mapping 'VX_alu_2_DW01_add_18' + Mapping 'VX_alu_2_DW01_add_19' + Mapping 'VX_alu_2_DW01_add_20' + Mapping 'VX_alu_2_DW01_add_21' + Mapping 'VX_alu_2_DW01_add_22' + Mapping 'VX_alu_2_DW01_add_23' + Mapping 'VX_alu_2_DW01_add_24' + Mapping 'VX_alu_2_DW01_add_25' + Mapping 'VX_alu_2_DW01_add_26' + Structuring 'VX_alu_2_DW_div_uns_1' + Mapping 'VX_alu_2_DW_div_uns_1' + Mapping 'VX_alu_2_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_28' + Mapping 'VX_alu_2_DW01_add_29' + Mapping 'VX_alu_2_DW01_add_30' + Mapping 'VX_alu_2_DW01_add_31' + Mapping 'VX_alu_2_DW01_add_32' + Mapping 'VX_alu_2_DW01_add_33' + Mapping 'VX_alu_2_DW01_add_34' + Mapping 'VX_alu_2_DW01_add_35' + Mapping 'VX_alu_2_DW01_add_36' + Mapping 'VX_alu_2_DW01_add_37' + Mapping 'VX_alu_2_DW01_add_38' + Mapping 'VX_alu_2_DW01_add_39' + Mapping 'VX_alu_2_DW01_add_40' + Mapping 'VX_alu_2_DW01_add_41' + Mapping 'VX_alu_2_DW01_add_42' + Mapping 'VX_alu_2_DW01_add_43' + Mapping 'VX_alu_2_DW01_add_44' + Mapping 'VX_alu_2_DW01_add_45' + Mapping 'VX_alu_2_DW01_add_46' + Mapping 'VX_alu_2_DW01_add_47' + Mapping 'VX_alu_2_DW01_add_48' + Mapping 'VX_alu_2_DW01_add_49' + Mapping 'VX_alu_2_DW01_add_50' + Mapping 'VX_alu_2_DW01_add_51' + Mapping 'VX_alu_2_DW01_add_52' + Mapping 'VX_alu_2_DW01_add_53' + Mapping 'VX_alu_2_DW01_add_54' + Mapping 'VX_alu_2_DW01_add_55' + Mapping 'VX_alu_2_DW01_add_56' + Mapping 'VX_alu_2_DW01_add_57' + Mapping 'VX_alu_2_DW01_add_58' + Mapping 'VX_alu_2_DW01_add_59' + Mapping 'VX_alu_2_DW01_add_60' + Mapping 'VX_alu_2_DW01_add_61' + Mapping 'VX_alu_2_DW01_add_62' + Mapping 'VX_alu_2_DW01_add_63' + Mapping 'VX_alu_2_DW01_add_64' + Mapping 'VX_alu_2_DW01_add_65' + Mapping 'VX_alu_2_DW01_add_66' + Structuring 'VX_alu_2_DW_div_uns_2' + Mapping 'VX_alu_2_DW_div_uns_2' + Mapping 'VX_alu_2_DW01_add_67' + Mapping 'VX_alu_2_DW01_add_68' + Mapping 'VX_alu_2_DW01_add_69' + Mapping 'VX_alu_2_DW01_sub_0' + Mapping 'VX_alu_2_DW01_add_70' + Mapping 'VX_alu_2_DW01_add_71' + Mapping 'VX_alu_2_DW01_add_72' + Mapping 'VX_alu_2_DW01_add_77' + Mapping 'VX_alu_2_DW01_add_78' + Mapping 'VX_alu_2_DW01_add_79' + Mapping 'VX_alu_2_DW01_add_80' + Mapping 'VX_alu_2_DW01_add_81' + Mapping 'VX_alu_2_DW01_add_82' + Mapping 'VX_alu_2_DW01_add_83' + Mapping 'VX_alu_2_DW01_add_84' + Mapping 'VX_alu_2_DW01_add_85' + Mapping 'VX_alu_2_DW01_add_86' + Mapping 'VX_alu_2_DW01_add_87' + Mapping 'VX_alu_2_DW01_add_88' + Mapping 'VX_alu_2_DW01_add_89' + Mapping 'VX_alu_2_DW01_add_90' + Mapping 'VX_alu_2_DW01_add_91' + Mapping 'VX_alu_2_DW01_add_92' + Mapping 'VX_alu_2_DW01_add_93' + Mapping 'VX_alu_2_DW01_add_94' + Mapping 'VX_alu_2_DW01_add_95' + Mapping 'VX_alu_2_DW01_add_96' + Mapping 'VX_alu_2_DW01_add_97' + Mapping 'VX_alu_2_DW01_add_98' + Mapping 'VX_alu_2_DW01_add_99' + Mapping 'VX_alu_2_DW01_add_100' + Mapping 'VX_alu_2_DW01_add_101' + Mapping 'VX_alu_2_DW01_add_102' + Mapping 'VX_alu_2_DW01_add_103' + Mapping 'VX_alu_2_DW01_add_104' + Mapping 'VX_alu_2_DW01_add_105' + Mapping 'VX_alu_2_DW01_add_106' + Mapping 'VX_alu_2_DW01_add_107' + Mapping 'VX_alu_2_DW01_add_108' + Mapping 'VX_alu_2_DW01_add_109' + Mapping 'VX_alu_2_DW01_add_110' + Mapping 'VX_alu_2_DW01_add_111' + Mapping 'VX_alu_2_DW01_add_112' + Mapping 'VX_alu_2_DW01_add_113' + Mapping 'VX_alu_2_DW01_add_114' + Mapping 'VX_alu_2_DW01_add_115' + Mapping 'VX_alu_2_DW01_add_116' + Mapping 'VX_alu_2_DW01_add_117' + Mapping 'VX_alu_2_DW01_add_118' + Mapping 'VX_alu_2_DW01_add_119' + Mapping 'VX_alu_2_DW01_add_120' + Mapping 'VX_alu_2_DW01_add_121' + Mapping 'VX_alu_2_DW01_add_122' + Mapping 'VX_alu_2_DW01_add_123' + Mapping 'VX_alu_2_DW01_add_124' + Mapping 'VX_alu_2_DW01_add_125' + Mapping 'VX_alu_2_DW01_add_126' + Mapping 'VX_alu_2_DW01_add_127' + Mapping 'VX_alu_2_DW01_add_128' + Mapping 'VX_alu_2_DW01_add_129' + Mapping 'VX_alu_2_DW01_add_130' + Mapping 'VX_alu_2_DW01_add_131' + Mapping 'VX_alu_2_DW01_add_132' + Mapping 'VX_alu_2_DW01_add_133' + Mapping 'VX_alu_2_DW01_add_134' + Mapping 'VX_alu_2_DW01_add_135' + Mapping 'VX_alu_2_DW01_add_136' + Mapping 'VX_alu_2_DW01_add_137' + Mapping 'VX_alu_2_DW01_add_138' + Mapping 'VX_alu_2_DW01_add_139' + Mapping 'VX_alu_2_DW01_add_140' + Mapping 'VX_alu_2_DW01_add_141' + Mapping 'VX_alu_2_DW01_add_142' + Mapping 'VX_alu_2_DW01_add_143' + Mapping 'VX_alu_2_DW01_add_144' + Mapping 'VX_alu_2_DW01_add_145' + Mapping 'VX_alu_2_DW01_add_146' + Structuring 'VX_alu_0_DW_div_tc_0' + Mapping 'VX_alu_0_DW_div_tc_0' + Structuring 'VX_alu_0_DW01_absval_0' + Mapping 'VX_alu_0_DW01_absval_0' + Structuring 'VX_alu_0_DW01_inc_0' + Mapping 'VX_alu_0_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_147' + Mapping 'VX_alu_0_DW01_add_148' + Mapping 'VX_alu_0_DW01_add_149' + Mapping 'VX_alu_0_DW01_add_150' + Mapping 'VX_alu_0_DW01_add_151' + Mapping 'VX_alu_0_DW01_add_152' + Mapping 'VX_alu_0_DW01_add_153' + Mapping 'VX_alu_0_DW01_add_154' + Mapping 'VX_alu_0_DW01_add_155' + Mapping 'VX_alu_0_DW01_add_156' + Mapping 'VX_alu_0_DW01_add_157' + Mapping 'VX_alu_0_DW01_add_158' + Mapping 'VX_alu_0_DW01_add_159' + Mapping 'VX_alu_0_DW01_add_160' + Mapping 'VX_alu_0_DW01_add_161' + Mapping 'VX_alu_0_DW01_add_162' + Mapping 'VX_alu_0_DW01_add_163' + Mapping 'VX_alu_0_DW01_add_164' + Mapping 'VX_alu_0_DW01_add_165' + Mapping 'VX_alu_0_DW01_add_166' + Mapping 'VX_alu_0_DW01_add_167' + Mapping 'VX_alu_0_DW01_add_168' + Mapping 'VX_alu_0_DW01_add_169' + Mapping 'VX_alu_0_DW01_add_170' + Mapping 'VX_alu_0_DW01_add_171' + Mapping 'VX_alu_0_DW01_add_172' + Mapping 'VX_alu_0_DW01_add_173' + Mapping 'VX_alu_0_DW_inc_1' + Structuring 'VX_alu_0_DW_div_tc_1' + Mapping 'VX_alu_0_DW_div_tc_1' + Structuring 'VX_alu_0_DW01_absval_1' + Mapping 'VX_alu_0_DW01_absval_1' + Structuring 'VX_alu_0_DW01_inc_1' + Mapping 'VX_alu_0_DW01_inc_1' + Mapping 'VX_alu_0_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_175' + Mapping 'VX_alu_0_DW01_add_176' + Mapping 'VX_alu_0_DW01_add_177' + Mapping 'VX_alu_0_DW01_add_178' + Mapping 'VX_alu_0_DW01_add_179' + Mapping 'VX_alu_0_DW01_add_180' + Mapping 'VX_alu_0_DW01_add_181' + Mapping 'VX_alu_0_DW01_add_182' + Mapping 'VX_alu_0_DW01_add_183' + Mapping 'VX_alu_0_DW01_add_184' + Mapping 'VX_alu_0_DW01_add_185' + Mapping 'VX_alu_0_DW01_add_186' + Mapping 'VX_alu_0_DW01_add_187' + Mapping 'VX_alu_0_DW01_add_188' + Mapping 'VX_alu_0_DW01_add_189' + Mapping 'VX_alu_0_DW01_add_190' + Mapping 'VX_alu_0_DW01_add_191' + Mapping 'VX_alu_0_DW01_add_192' + Mapping 'VX_alu_0_DW01_add_193' + Mapping 'VX_alu_0_DW01_add_194' + Mapping 'VX_alu_0_DW01_add_195' + Mapping 'VX_alu_0_DW01_add_196' + Mapping 'VX_alu_0_DW01_add_197' + Mapping 'VX_alu_0_DW01_add_198' + Mapping 'VX_alu_0_DW01_add_199' + Mapping 'VX_alu_0_DW01_add_200' + Mapping 'VX_alu_0_DW01_add_201' + Mapping 'VX_alu_0_DW01_add_202' + Mapping 'VX_alu_0_DW01_add_203' + Mapping 'VX_alu_0_DW01_add_204' + Mapping 'VX_alu_0_DW01_add_205' + Mapping 'VX_alu_0_DW01_add_206' + Mapping 'VX_alu_0_DW01_add_207' + Mapping 'VX_alu_0_DW01_add_208' + Mapping 'VX_alu_0_DW01_add_209' + Mapping 'VX_alu_0_DW01_add_210' + Mapping 'VX_alu_0_DW01_add_211' + Mapping 'VX_alu_0_DW01_add_212' + Mapping 'VX_alu_0_DW01_add_213' + Mapping 'VX_alu_0_DW_inc_3' + Structuring 'VX_alu_0_DW_div_tc_2' + Mapping 'VX_alu_0_DW_div_tc_2' + Structuring 'VX_alu_0_DW01_absval_2' + Mapping 'VX_alu_0_DW01_absval_2' + Structuring 'VX_alu_0_DW01_inc_2' + Mapping 'VX_alu_0_DW01_inc_2' + Mapping 'VX_alu_0_DW01_add_214' + Mapping 'VX_alu_0_DW01_add_215' + Mapping 'VX_alu_0_DW01_add_216' + Mapping 'VX_alu_0_DW01_sub_1' + Mapping 'VX_alu_0_DW01_add_217' + Mapping 'VX_alu_0_DW01_add_218' + Mapping 'VX_alu_0_DW01_add_219' + Mapping 'VX_alu_0_DW01_add_224' + Mapping 'VX_alu_0_DW01_add_225' + Mapping 'VX_alu_0_DW01_add_226' + Mapping 'VX_alu_0_DW01_add_227' + Mapping 'VX_alu_0_DW01_add_228' + Mapping 'VX_alu_0_DW01_add_229' + Mapping 'VX_alu_0_DW01_add_230' + Mapping 'VX_alu_0_DW01_add_231' + Mapping 'VX_alu_0_DW01_add_232' + Mapping 'VX_alu_0_DW01_add_233' + Mapping 'VX_alu_0_DW01_add_234' + Mapping 'VX_alu_0_DW01_add_235' + Mapping 'VX_alu_0_DW01_add_236' + Mapping 'VX_alu_0_DW01_add_237' + Mapping 'VX_alu_0_DW01_add_238' + Mapping 'VX_alu_0_DW01_add_239' + Mapping 'VX_alu_0_DW01_add_240' + Mapping 'VX_alu_0_DW01_add_241' + Mapping 'VX_alu_0_DW01_add_242' + Mapping 'VX_alu_0_DW01_add_243' + Mapping 'VX_alu_0_DW01_add_244' + Mapping 'VX_alu_0_DW01_add_245' + Mapping 'VX_alu_0_DW01_add_246' + Mapping 'VX_alu_0_DW01_add_247' + Mapping 'VX_alu_0_DW01_add_248' + Mapping 'VX_alu_0_DW01_add_249' + Mapping 'VX_alu_0_DW01_add_250' + Mapping 'VX_alu_0_DW01_add_251' + Mapping 'VX_alu_0_DW01_add_252' + Mapping 'VX_alu_0_DW01_add_253' + Mapping 'VX_alu_0_DW01_add_254' + Mapping 'VX_alu_0_DW01_add_255' + Mapping 'VX_alu_0_DW01_add_256' + Mapping 'VX_alu_0_DW01_add_257' + Mapping 'VX_alu_0_DW01_add_258' + Mapping 'VX_alu_0_DW01_add_259' + Mapping 'VX_alu_0_DW01_add_260' + Mapping 'VX_alu_0_DW01_add_261' + Mapping 'VX_alu_0_DW01_add_262' + Mapping 'VX_alu_0_DW01_add_263' + Mapping 'VX_alu_0_DW01_add_264' + Mapping 'VX_alu_0_DW01_add_265' + Mapping 'VX_alu_0_DW01_add_266' + Mapping 'VX_alu_0_DW01_add_267' + Mapping 'VX_alu_0_DW01_add_268' + Mapping 'VX_alu_0_DW01_add_269' + Mapping 'VX_alu_0_DW01_add_270' + Mapping 'VX_alu_0_DW01_add_271' + Mapping 'VX_alu_0_DW01_add_272' + Mapping 'VX_alu_0_DW01_add_273' + Mapping 'VX_alu_0_DW01_add_274' + Mapping 'VX_alu_0_DW01_add_275' + Mapping 'VX_alu_0_DW01_add_276' + Mapping 'VX_alu_0_DW01_add_277' + Mapping 'VX_alu_0_DW01_add_278' + Mapping 'VX_alu_0_DW01_add_279' + Mapping 'VX_alu_0_DW01_add_280' + Mapping 'VX_alu_0_DW01_add_281' + Mapping 'VX_alu_0_DW01_add_282' + Mapping 'VX_alu_0_DW01_add_283' + Mapping 'VX_alu_0_DW01_add_284' + Mapping 'VX_alu_0_DW01_add_285' + Mapping 'VX_alu_0_DW01_add_286' + Mapping 'VX_alu_0_DW01_add_287' + Mapping 'VX_alu_0_DW01_add_288' + Mapping 'VX_alu_0_DW01_add_289' + Mapping 'VX_alu_0_DW01_add_290' + Mapping 'VX_alu_0_DW01_add_291' + Mapping 'VX_alu_0_DW01_add_292' + Mapping 'VX_alu_0_DW01_add_293' + Mapping 'VX_alu_0_DW_inc_5' + Structuring 'VX_alu_1_DW_div_tc_0' + Mapping 'VX_alu_1_DW_div_tc_0' + Structuring 'VX_alu_1_DW01_absval_0' + Mapping 'VX_alu_1_DW01_absval_0' + Structuring 'VX_alu_1_DW01_inc_0' + Mapping 'VX_alu_1_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_147' + Mapping 'VX_alu_1_DW01_add_148' + Mapping 'VX_alu_1_DW01_add_149' + Mapping 'VX_alu_1_DW01_add_150' + Mapping 'VX_alu_1_DW01_add_151' + Mapping 'VX_alu_1_DW01_add_152' + Mapping 'VX_alu_1_DW01_add_153' + Mapping 'VX_alu_1_DW01_add_154' + Mapping 'VX_alu_1_DW01_add_155' + Mapping 'VX_alu_1_DW01_add_156' + Mapping 'VX_alu_1_DW01_add_157' + Mapping 'VX_alu_1_DW01_add_158' + Mapping 'VX_alu_1_DW01_add_159' + Mapping 'VX_alu_1_DW01_add_160' + Mapping 'VX_alu_1_DW01_add_161' + Mapping 'VX_alu_1_DW01_add_162' + Mapping 'VX_alu_1_DW01_add_163' + Mapping 'VX_alu_1_DW01_add_164' + Mapping 'VX_alu_1_DW01_add_165' + Mapping 'VX_alu_1_DW01_add_166' + Mapping 'VX_alu_1_DW01_add_167' + Mapping 'VX_alu_1_DW01_add_168' + Mapping 'VX_alu_1_DW01_add_169' + Mapping 'VX_alu_1_DW01_add_170' + Mapping 'VX_alu_1_DW01_add_171' + Mapping 'VX_alu_1_DW01_add_172' + Mapping 'VX_alu_1_DW01_add_173' + Mapping 'VX_alu_1_DW_inc_1' + Structuring 'VX_alu_1_DW_div_tc_1' + Mapping 'VX_alu_1_DW_div_tc_1' + Structuring 'VX_alu_1_DW01_absval_1' + Mapping 'VX_alu_1_DW01_absval_1' + Structuring 'VX_alu_1_DW01_inc_1' + Mapping 'VX_alu_1_DW01_inc_1' + Mapping 'VX_alu_1_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_175' + Mapping 'VX_alu_1_DW01_add_176' + Mapping 'VX_alu_1_DW01_add_177' + Mapping 'VX_alu_1_DW01_add_178' + Mapping 'VX_alu_1_DW01_add_179' + Mapping 'VX_alu_1_DW01_add_180' + Mapping 'VX_alu_1_DW01_add_181' + Mapping 'VX_alu_1_DW01_add_182' + Mapping 'VX_alu_1_DW01_add_183' + Mapping 'VX_alu_1_DW01_add_184' + Mapping 'VX_alu_1_DW01_add_185' + Mapping 'VX_alu_1_DW01_add_186' + Mapping 'VX_alu_1_DW01_add_187' + Mapping 'VX_alu_1_DW01_add_188' + Mapping 'VX_alu_1_DW01_add_189' + Mapping 'VX_alu_1_DW01_add_190' + Mapping 'VX_alu_1_DW01_add_191' + Mapping 'VX_alu_1_DW01_add_192' + Mapping 'VX_alu_1_DW01_add_193' + Mapping 'VX_alu_1_DW01_add_194' + Mapping 'VX_alu_1_DW01_add_195' + Mapping 'VX_alu_1_DW01_add_196' + Mapping 'VX_alu_1_DW01_add_197' + Mapping 'VX_alu_1_DW01_add_198' + Mapping 'VX_alu_1_DW01_add_199' + Mapping 'VX_alu_1_DW01_add_200' + Mapping 'VX_alu_1_DW01_add_201' + Mapping 'VX_alu_1_DW01_add_202' + Mapping 'VX_alu_1_DW01_add_203' + Mapping 'VX_alu_1_DW01_add_204' + Mapping 'VX_alu_1_DW01_add_205' + Mapping 'VX_alu_1_DW01_add_206' + Mapping 'VX_alu_1_DW01_add_207' + Mapping 'VX_alu_1_DW01_add_208' + Mapping 'VX_alu_1_DW01_add_209' + Mapping 'VX_alu_1_DW01_add_210' + Mapping 'VX_alu_1_DW01_add_211' + Mapping 'VX_alu_1_DW01_add_212' + Mapping 'VX_alu_1_DW01_add_213' + Mapping 'VX_alu_1_DW_inc_3' + Structuring 'VX_alu_1_DW_div_tc_2' + Mapping 'VX_alu_1_DW_div_tc_2' + Structuring 'VX_alu_1_DW01_absval_2' + Mapping 'VX_alu_1_DW01_absval_2' + Structuring 'VX_alu_1_DW01_inc_2' + Mapping 'VX_alu_1_DW01_inc_2' + Mapping 'VX_alu_1_DW01_add_214' + Mapping 'VX_alu_1_DW01_add_215' + Mapping 'VX_alu_1_DW01_add_216' + Mapping 'VX_alu_1_DW01_sub_1' + Mapping 'VX_alu_1_DW01_add_217' + Mapping 'VX_alu_1_DW01_add_218' + Mapping 'VX_alu_1_DW01_add_219' + Mapping 'VX_alu_1_DW01_add_224' + Mapping 'VX_alu_1_DW01_add_225' + Mapping 'VX_alu_1_DW01_add_226' + Mapping 'VX_alu_1_DW01_add_227' + Mapping 'VX_alu_1_DW01_add_228' + Mapping 'VX_alu_1_DW01_add_229' + Mapping 'VX_alu_1_DW01_add_230' + Mapping 'VX_alu_1_DW01_add_231' + Mapping 'VX_alu_1_DW01_add_232' + Mapping 'VX_alu_1_DW01_add_233' + Mapping 'VX_alu_1_DW01_add_234' + Mapping 'VX_alu_1_DW01_add_235' + Mapping 'VX_alu_1_DW01_add_236' + Mapping 'VX_alu_1_DW01_add_237' + Mapping 'VX_alu_1_DW01_add_238' + Mapping 'VX_alu_1_DW01_add_239' + Mapping 'VX_alu_1_DW01_add_240' + Mapping 'VX_alu_1_DW01_add_241' + Mapping 'VX_alu_1_DW01_add_242' + Mapping 'VX_alu_1_DW01_add_243' + Mapping 'VX_alu_1_DW01_add_244' + Mapping 'VX_alu_1_DW01_add_245' + Mapping 'VX_alu_1_DW01_add_246' + Mapping 'VX_alu_1_DW01_add_247' + Mapping 'VX_alu_1_DW01_add_248' + Mapping 'VX_alu_1_DW01_add_249' + Mapping 'VX_alu_1_DW01_add_250' + Mapping 'VX_alu_1_DW01_add_251' + Mapping 'VX_alu_1_DW01_add_252' + Mapping 'VX_alu_1_DW01_add_253' + Mapping 'VX_alu_1_DW01_add_254' + Mapping 'VX_alu_1_DW01_add_255' + Mapping 'VX_alu_1_DW01_add_256' + Mapping 'VX_alu_1_DW01_add_257' + Mapping 'VX_alu_1_DW01_add_258' + Mapping 'VX_alu_1_DW01_add_259' + Mapping 'VX_alu_1_DW01_add_260' + Mapping 'VX_alu_1_DW01_add_261' + Mapping 'VX_alu_1_DW01_add_262' + Mapping 'VX_alu_1_DW01_add_263' + Mapping 'VX_alu_1_DW01_add_264' + Mapping 'VX_alu_1_DW01_add_265' + Mapping 'VX_alu_1_DW01_add_266' + Mapping 'VX_alu_1_DW01_add_267' + Mapping 'VX_alu_1_DW01_add_268' + Mapping 'VX_alu_1_DW01_add_269' + Mapping 'VX_alu_1_DW01_add_270' + Mapping 'VX_alu_1_DW01_add_271' + Mapping 'VX_alu_1_DW01_add_272' + Mapping 'VX_alu_1_DW01_add_273' + Mapping 'VX_alu_1_DW01_add_274' + Mapping 'VX_alu_1_DW01_add_275' + Mapping 'VX_alu_1_DW01_add_276' + Mapping 'VX_alu_1_DW01_add_277' + Mapping 'VX_alu_1_DW01_add_278' + Mapping 'VX_alu_1_DW01_add_279' + Mapping 'VX_alu_1_DW01_add_280' + Mapping 'VX_alu_1_DW01_add_281' + Mapping 'VX_alu_1_DW01_add_282' + Mapping 'VX_alu_1_DW01_add_283' + Mapping 'VX_alu_1_DW01_add_284' + Mapping 'VX_alu_1_DW01_add_285' + Mapping 'VX_alu_1_DW01_add_286' + Mapping 'VX_alu_1_DW01_add_287' + Mapping 'VX_alu_1_DW01_add_288' + Mapping 'VX_alu_1_DW01_add_289' + Mapping 'VX_alu_1_DW01_add_290' + Mapping 'VX_alu_1_DW01_add_291' + Mapping 'VX_alu_1_DW01_add_292' + Mapping 'VX_alu_1_DW01_add_293' + Mapping 'VX_alu_1_DW_inc_5' + Structuring 'VX_alu_2_DW_div_tc_0' + Mapping 'VX_alu_2_DW_div_tc_0' + Structuring 'VX_alu_2_DW01_absval_0' + Mapping 'VX_alu_2_DW01_absval_0' + Structuring 'VX_alu_2_DW01_inc_0' + Mapping 'VX_alu_2_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_147' + Mapping 'VX_alu_2_DW01_add_148' + Mapping 'VX_alu_2_DW01_add_149' + Mapping 'VX_alu_2_DW01_add_150' + Mapping 'VX_alu_2_DW01_add_151' + Mapping 'VX_alu_2_DW01_add_152' + Mapping 'VX_alu_2_DW01_add_153' + Mapping 'VX_alu_2_DW01_add_154' + Mapping 'VX_alu_2_DW01_add_155' + Mapping 'VX_alu_2_DW01_add_156' + Mapping 'VX_alu_2_DW01_add_157' + Mapping 'VX_alu_2_DW01_add_158' + Mapping 'VX_alu_2_DW01_add_159' + Mapping 'VX_alu_2_DW01_add_160' + Mapping 'VX_alu_2_DW01_add_161' + Mapping 'VX_alu_2_DW01_add_162' + Mapping 'VX_alu_2_DW01_add_163' + Mapping 'VX_alu_2_DW01_add_164' + Mapping 'VX_alu_2_DW01_add_165' + Mapping 'VX_alu_2_DW01_add_166' + Mapping 'VX_alu_2_DW01_add_167' + Mapping 'VX_alu_2_DW01_add_168' + Mapping 'VX_alu_2_DW01_add_169' + Mapping 'VX_alu_2_DW01_add_170' + Mapping 'VX_alu_2_DW01_add_171' + Mapping 'VX_alu_2_DW01_add_172' + Mapping 'VX_alu_2_DW01_add_173' + Mapping 'VX_alu_2_DW_inc_1' + Structuring 'VX_alu_2_DW_div_tc_1' + Mapping 'VX_alu_2_DW_div_tc_1' + Structuring 'VX_alu_2_DW01_absval_1' + Mapping 'VX_alu_2_DW01_absval_1' + Structuring 'VX_alu_2_DW01_inc_1' + Mapping 'VX_alu_2_DW01_inc_1' + Mapping 'VX_alu_2_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_175' + Mapping 'VX_alu_2_DW01_add_176' + Mapping 'VX_alu_2_DW01_add_177' + Mapping 'VX_alu_2_DW01_add_178' + Mapping 'VX_alu_2_DW01_add_179' + Mapping 'VX_alu_2_DW01_add_180' + Mapping 'VX_alu_2_DW01_add_181' + Mapping 'VX_alu_2_DW01_add_182' + Mapping 'VX_alu_2_DW01_add_183' + Mapping 'VX_alu_2_DW01_add_184' + Mapping 'VX_alu_2_DW01_add_185' + Mapping 'VX_alu_2_DW01_add_186' + Mapping 'VX_alu_2_DW01_add_187' + Mapping 'VX_alu_2_DW01_add_188' + Mapping 'VX_alu_2_DW01_add_189' + Mapping 'VX_alu_2_DW01_add_190' + Mapping 'VX_alu_2_DW01_add_191' + Mapping 'VX_alu_2_DW01_add_192' + Mapping 'VX_alu_2_DW01_add_193' + Mapping 'VX_alu_2_DW01_add_194' + Mapping 'VX_alu_2_DW01_add_195' + Mapping 'VX_alu_2_DW01_add_196' + Mapping 'VX_alu_2_DW01_add_197' + Mapping 'VX_alu_2_DW01_add_198' + Mapping 'VX_alu_2_DW01_add_199' + Mapping 'VX_alu_2_DW01_add_200' + Mapping 'VX_alu_2_DW01_add_201' + Mapping 'VX_alu_2_DW01_add_202' + Mapping 'VX_alu_2_DW01_add_203' + Mapping 'VX_alu_2_DW01_add_204' + Mapping 'VX_alu_2_DW01_add_205' + Mapping 'VX_alu_2_DW01_add_206' + Mapping 'VX_alu_2_DW01_add_207' + Mapping 'VX_alu_2_DW01_add_208' + Mapping 'VX_alu_2_DW01_add_209' + Mapping 'VX_alu_2_DW01_add_210' + Mapping 'VX_alu_2_DW01_add_211' + Mapping 'VX_alu_2_DW01_add_212' + Mapping 'VX_alu_2_DW01_add_213' + Mapping 'VX_alu_2_DW_inc_3' + Structuring 'VX_alu_2_DW_div_tc_2' + Mapping 'VX_alu_2_DW_div_tc_2' + Structuring 'VX_alu_2_DW01_absval_2' + Mapping 'VX_alu_2_DW01_absval_2' + Structuring 'VX_alu_2_DW01_inc_2' + Mapping 'VX_alu_2_DW01_inc_2' + Mapping 'VX_alu_2_DW01_add_214' + Mapping 'VX_alu_2_DW01_add_215' + Mapping 'VX_alu_2_DW01_add_216' + Mapping 'VX_alu_2_DW01_sub_1' + Mapping 'VX_alu_2_DW01_add_217' + Mapping 'VX_alu_2_DW01_add_218' + Mapping 'VX_alu_2_DW01_add_219' + Mapping 'VX_alu_2_DW01_add_224' + Mapping 'VX_alu_2_DW01_add_225' + Mapping 'VX_alu_2_DW01_add_226' + Mapping 'VX_alu_2_DW01_add_227' + Mapping 'VX_alu_2_DW01_add_228' + Mapping 'VX_alu_2_DW01_add_229' + Mapping 'VX_alu_2_DW01_add_230' + Mapping 'VX_alu_2_DW01_add_231' + Mapping 'VX_alu_2_DW01_add_232' + Mapping 'VX_alu_2_DW01_add_233' + Mapping 'VX_alu_2_DW01_add_234' + Mapping 'VX_alu_2_DW01_add_235' + Mapping 'VX_alu_2_DW01_add_236' + Mapping 'VX_alu_2_DW01_add_237' + Mapping 'VX_alu_2_DW01_add_238' + Mapping 'VX_alu_2_DW01_add_239' + Mapping 'VX_alu_2_DW01_add_240' + Mapping 'VX_alu_2_DW01_add_241' + Mapping 'VX_alu_2_DW01_add_242' + Mapping 'VX_alu_2_DW01_add_243' + Mapping 'VX_alu_2_DW01_add_244' + Mapping 'VX_alu_2_DW01_add_245' + Mapping 'VX_alu_2_DW01_add_246' + Mapping 'VX_alu_2_DW01_add_247' + Mapping 'VX_alu_2_DW01_add_248' + Mapping 'VX_alu_2_DW01_add_249' + Mapping 'VX_alu_2_DW01_add_250' + Mapping 'VX_alu_2_DW01_add_251' + Mapping 'VX_alu_2_DW01_add_252' + Mapping 'VX_alu_2_DW01_add_253' + Mapping 'VX_alu_2_DW01_add_254' + Mapping 'VX_alu_2_DW01_add_255' + Mapping 'VX_alu_2_DW01_add_256' + Mapping 'VX_alu_2_DW01_add_257' + Mapping 'VX_alu_2_DW01_add_258' + Mapping 'VX_alu_2_DW01_add_259' + Mapping 'VX_alu_2_DW01_add_260' + Mapping 'VX_alu_2_DW01_add_261' + Mapping 'VX_alu_2_DW01_add_262' + Mapping 'VX_alu_2_DW01_add_263' + Mapping 'VX_alu_2_DW01_add_264' + Mapping 'VX_alu_2_DW01_add_265' + Mapping 'VX_alu_2_DW01_add_266' + Mapping 'VX_alu_2_DW01_add_267' + Mapping 'VX_alu_2_DW01_add_268' + Mapping 'VX_alu_2_DW01_add_269' + Mapping 'VX_alu_2_DW01_add_270' + Mapping 'VX_alu_2_DW01_add_271' + Mapping 'VX_alu_2_DW01_add_272' + Mapping 'VX_alu_2_DW01_add_273' + Mapping 'VX_alu_2_DW01_add_274' + Mapping 'VX_alu_2_DW01_add_275' + Mapping 'VX_alu_2_DW01_add_276' + Mapping 'VX_alu_2_DW01_add_277' + Mapping 'VX_alu_2_DW01_add_278' + Mapping 'VX_alu_2_DW01_add_279' + Mapping 'VX_alu_2_DW01_add_280' + Mapping 'VX_alu_2_DW01_add_281' + Mapping 'VX_alu_2_DW01_add_282' + Mapping 'VX_alu_2_DW01_add_283' + Mapping 'VX_alu_2_DW01_add_284' + Mapping 'VX_alu_2_DW01_add_285' + Mapping 'VX_alu_2_DW01_add_286' + Mapping 'VX_alu_2_DW01_add_287' + Mapping 'VX_alu_2_DW01_add_288' + Mapping 'VX_alu_2_DW01_add_289' + Mapping 'VX_alu_2_DW01_add_290' + Mapping 'VX_alu_2_DW01_add_291' + Mapping 'VX_alu_2_DW01_add_292' + Mapping 'VX_alu_2_DW01_add_293' + Mapping 'VX_alu_2_DW_inc_5' + Structuring 'VX_alu_0_DW_div_uns_3' + Mapping 'VX_alu_0_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_294' + Mapping 'VX_alu_0_DW01_add_295' + Mapping 'VX_alu_0_DW01_add_296' + Mapping 'VX_alu_0_DW01_add_297' + Mapping 'VX_alu_0_DW01_add_298' + Mapping 'VX_alu_0_DW01_add_299' + Mapping 'VX_alu_0_DW01_add_300' + Mapping 'VX_alu_0_DW01_add_301' + Mapping 'VX_alu_0_DW01_add_302' + Mapping 'VX_alu_0_DW01_add_303' + Mapping 'VX_alu_0_DW01_add_304' + Mapping 'VX_alu_0_DW01_add_305' + Mapping 'VX_alu_0_DW01_add_306' + Mapping 'VX_alu_0_DW01_add_307' + Mapping 'VX_alu_0_DW01_add_308' + Mapping 'VX_alu_0_DW01_add_309' + Mapping 'VX_alu_0_DW01_add_310' + Mapping 'VX_alu_0_DW01_add_311' + Mapping 'VX_alu_0_DW01_add_312' + Mapping 'VX_alu_0_DW01_add_313' + Mapping 'VX_alu_0_DW01_add_314' + Mapping 'VX_alu_0_DW01_add_315' + Mapping 'VX_alu_0_DW01_add_316' + Mapping 'VX_alu_0_DW01_add_317' + Mapping 'VX_alu_0_DW01_add_318' + Mapping 'VX_alu_0_DW01_add_319' + Mapping 'VX_alu_0_DW01_add_320' + Structuring 'VX_alu_0_DW_div_uns_4' + Mapping 'VX_alu_0_DW_div_uns_4' + Mapping 'VX_alu_0_DW01_add_321' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_322' + Mapping 'VX_alu_0_DW01_add_323' + Mapping 'VX_alu_0_DW01_add_324' + Mapping 'VX_alu_0_DW01_add_325' + Mapping 'VX_alu_0_DW01_add_326' + Mapping 'VX_alu_0_DW01_add_327' + Mapping 'VX_alu_0_DW01_add_328' + Mapping 'VX_alu_0_DW01_add_329' + Mapping 'VX_alu_0_DW01_add_330' + Mapping 'VX_alu_0_DW01_add_331' + Mapping 'VX_alu_0_DW01_add_332' + Mapping 'VX_alu_0_DW01_add_333' + Mapping 'VX_alu_0_DW01_add_334' + Mapping 'VX_alu_0_DW01_add_335' + Mapping 'VX_alu_0_DW01_add_336' + Mapping 'VX_alu_0_DW01_add_337' + Mapping 'VX_alu_0_DW01_add_338' + Mapping 'VX_alu_0_DW01_add_339' + Mapping 'VX_alu_0_DW01_add_340' + Mapping 'VX_alu_0_DW01_add_341' + Mapping 'VX_alu_0_DW01_add_342' + Mapping 'VX_alu_0_DW01_add_343' + Mapping 'VX_alu_0_DW01_add_344' + Mapping 'VX_alu_0_DW01_add_345' + Mapping 'VX_alu_0_DW01_add_346' + Mapping 'VX_alu_0_DW01_add_347' + Mapping 'VX_alu_0_DW01_add_348' + Mapping 'VX_alu_0_DW01_add_349' + Mapping 'VX_alu_0_DW01_add_350' + Mapping 'VX_alu_0_DW01_add_351' + Mapping 'VX_alu_0_DW01_add_352' + Mapping 'VX_alu_0_DW01_add_353' + Mapping 'VX_alu_0_DW01_add_354' + Mapping 'VX_alu_0_DW01_add_355' + Mapping 'VX_alu_0_DW01_add_356' + Mapping 'VX_alu_0_DW01_add_357' + Mapping 'VX_alu_0_DW01_add_358' + Mapping 'VX_alu_0_DW01_add_359' + Mapping 'VX_alu_0_DW01_add_360' + Structuring 'VX_alu_0_DW_div_uns_5' + Mapping 'VX_alu_0_DW_div_uns_5' + Mapping 'VX_alu_0_DW01_add_361' + Mapping 'VX_alu_0_DW01_add_362' + Mapping 'VX_alu_0_DW01_add_363' + Mapping 'VX_alu_0_DW01_sub_2' + Mapping 'VX_alu_0_DW01_add_364' + Mapping 'VX_alu_0_DW01_add_365' + Mapping 'VX_alu_0_DW01_add_366' + Mapping 'VX_alu_0_DW01_add_371' + Mapping 'VX_alu_0_DW01_add_372' + Mapping 'VX_alu_0_DW01_add_373' + Mapping 'VX_alu_0_DW01_add_374' + Mapping 'VX_alu_0_DW01_add_375' + Mapping 'VX_alu_0_DW01_add_376' + Mapping 'VX_alu_0_DW01_add_377' + Mapping 'VX_alu_0_DW01_add_378' + Mapping 'VX_alu_0_DW01_add_379' + Mapping 'VX_alu_0_DW01_add_380' + Mapping 'VX_alu_0_DW01_add_381' + Mapping 'VX_alu_0_DW01_add_382' + Mapping 'VX_alu_0_DW01_add_383' + Mapping 'VX_alu_0_DW01_add_384' + Mapping 'VX_alu_0_DW01_add_385' + Mapping 'VX_alu_0_DW01_add_386' + Mapping 'VX_alu_0_DW01_add_387' + Mapping 'VX_alu_0_DW01_add_388' + Mapping 'VX_alu_0_DW01_add_389' + Mapping 'VX_alu_0_DW01_add_390' + Mapping 'VX_alu_0_DW01_add_391' + Mapping 'VX_alu_0_DW01_add_392' + Mapping 'VX_alu_0_DW01_add_393' + Mapping 'VX_alu_0_DW01_add_394' + Mapping 'VX_alu_0_DW01_add_395' + Mapping 'VX_alu_0_DW01_add_396' + Mapping 'VX_alu_0_DW01_add_397' + Mapping 'VX_alu_0_DW01_add_398' + Mapping 'VX_alu_0_DW01_add_399' + Mapping 'VX_alu_0_DW01_add_400' + Mapping 'VX_alu_0_DW01_add_401' + Mapping 'VX_alu_0_DW01_add_402' + Mapping 'VX_alu_0_DW01_add_403' + Mapping 'VX_alu_0_DW01_add_404' + Mapping 'VX_alu_0_DW01_add_405' + Mapping 'VX_alu_0_DW01_add_406' + Mapping 'VX_alu_0_DW01_add_407' + Mapping 'VX_alu_0_DW01_add_408' + Mapping 'VX_alu_0_DW01_add_409' + Mapping 'VX_alu_0_DW01_add_410' + Mapping 'VX_alu_0_DW01_add_411' + Mapping 'VX_alu_0_DW01_add_412' + Mapping 'VX_alu_0_DW01_add_413' + Mapping 'VX_alu_0_DW01_add_414' + Mapping 'VX_alu_0_DW01_add_415' + Mapping 'VX_alu_0_DW01_add_416' + Mapping 'VX_alu_0_DW01_add_417' + Mapping 'VX_alu_0_DW01_add_418' + Mapping 'VX_alu_0_DW01_add_419' + Mapping 'VX_alu_0_DW01_add_420' + Mapping 'VX_alu_0_DW01_add_421' + Mapping 'VX_alu_0_DW01_add_422' + Mapping 'VX_alu_0_DW01_add_423' + Mapping 'VX_alu_0_DW01_add_424' + Mapping 'VX_alu_0_DW01_add_425' + Mapping 'VX_alu_0_DW01_add_426' + Mapping 'VX_alu_0_DW01_add_427' + Mapping 'VX_alu_0_DW01_add_428' + Mapping 'VX_alu_0_DW01_add_429' + Mapping 'VX_alu_0_DW01_add_430' + Mapping 'VX_alu_0_DW01_add_431' + Mapping 'VX_alu_0_DW01_add_432' + Mapping 'VX_alu_0_DW01_add_433' + Mapping 'VX_alu_0_DW01_add_434' + Mapping 'VX_alu_0_DW01_add_435' + Mapping 'VX_alu_0_DW01_add_436' + Mapping 'VX_alu_0_DW01_add_437' + Mapping 'VX_alu_0_DW01_add_438' + Mapping 'VX_alu_0_DW01_add_439' + Mapping 'VX_alu_0_DW01_add_440' + Structuring 'VX_alu_1_DW_div_uns_3' + Mapping 'VX_alu_1_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_294' + Mapping 'VX_alu_1_DW01_add_295' + Mapping 'VX_alu_1_DW01_add_296' + Mapping 'VX_alu_1_DW01_add_297' + Mapping 'VX_alu_1_DW01_add_298' + Mapping 'VX_alu_1_DW01_add_299' + Mapping 'VX_alu_1_DW01_add_300' + Mapping 'VX_alu_1_DW01_add_301' + Mapping 'VX_alu_1_DW01_add_302' + Mapping 'VX_alu_1_DW01_add_303' + Mapping 'VX_alu_1_DW01_add_304' + Mapping 'VX_alu_1_DW01_add_305' + Mapping 'VX_alu_1_DW01_add_306' + Mapping 'VX_alu_1_DW01_add_307' + Mapping 'VX_alu_1_DW01_add_308' + Mapping 'VX_alu_1_DW01_add_309' + Mapping 'VX_alu_1_DW01_add_310' + Mapping 'VX_alu_1_DW01_add_311' + Mapping 'VX_alu_1_DW01_add_312' + Mapping 'VX_alu_1_DW01_add_313' + Mapping 'VX_alu_1_DW01_add_314' + Mapping 'VX_alu_1_DW01_add_315' + Mapping 'VX_alu_1_DW01_add_316' + Mapping 'VX_alu_1_DW01_add_317' + Mapping 'VX_alu_1_DW01_add_318' + Mapping 'VX_alu_1_DW01_add_319' + Mapping 'VX_alu_1_DW01_add_320' + Structuring 'VX_alu_1_DW_div_uns_4' + Mapping 'VX_alu_1_DW_div_uns_4' + Mapping 'VX_alu_1_DW01_add_321' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_322' + Mapping 'VX_alu_1_DW01_add_323' + Mapping 'VX_alu_1_DW01_add_324' + Mapping 'VX_alu_1_DW01_add_325' + Mapping 'VX_alu_1_DW01_add_326' + Mapping 'VX_alu_1_DW01_add_327' + Mapping 'VX_alu_1_DW01_add_328' + Mapping 'VX_alu_1_DW01_add_329' + Mapping 'VX_alu_1_DW01_add_330' + Mapping 'VX_alu_1_DW01_add_331' + Mapping 'VX_alu_1_DW01_add_332' + Mapping 'VX_alu_1_DW01_add_333' + Mapping 'VX_alu_1_DW01_add_334' + Mapping 'VX_alu_1_DW01_add_335' + Mapping 'VX_alu_1_DW01_add_336' + Mapping 'VX_alu_1_DW01_add_337' + Mapping 'VX_alu_1_DW01_add_338' + Mapping 'VX_alu_1_DW01_add_339' + Mapping 'VX_alu_1_DW01_add_340' + Mapping 'VX_alu_1_DW01_add_341' + Mapping 'VX_alu_1_DW01_add_342' + Mapping 'VX_alu_1_DW01_add_343' + Mapping 'VX_alu_1_DW01_add_344' + Mapping 'VX_alu_1_DW01_add_345' + Mapping 'VX_alu_1_DW01_add_346' + Mapping 'VX_alu_1_DW01_add_347' + Mapping 'VX_alu_1_DW01_add_348' + Mapping 'VX_alu_1_DW01_add_349' + Mapping 'VX_alu_1_DW01_add_350' + Mapping 'VX_alu_1_DW01_add_351' + Mapping 'VX_alu_1_DW01_add_352' + Mapping 'VX_alu_1_DW01_add_353' + Mapping 'VX_alu_1_DW01_add_354' + Mapping 'VX_alu_1_DW01_add_355' + Mapping 'VX_alu_1_DW01_add_356' + Mapping 'VX_alu_1_DW01_add_357' + Mapping 'VX_alu_1_DW01_add_358' + Mapping 'VX_alu_1_DW01_add_359' + Mapping 'VX_alu_1_DW01_add_360' + Structuring 'VX_alu_1_DW_div_uns_5' + Mapping 'VX_alu_1_DW_div_uns_5' + Mapping 'VX_alu_1_DW01_add_361' + Mapping 'VX_alu_1_DW01_add_362' + Mapping 'VX_alu_1_DW01_add_363' + Mapping 'VX_alu_1_DW01_sub_2' + Mapping 'VX_alu_1_DW01_add_364' + Mapping 'VX_alu_1_DW01_add_365' + Mapping 'VX_alu_1_DW01_add_366' + Mapping 'VX_alu_1_DW01_add_371' + Mapping 'VX_alu_1_DW01_add_372' + Mapping 'VX_alu_1_DW01_add_373' + Mapping 'VX_alu_1_DW01_add_374' + Mapping 'VX_alu_1_DW01_add_375' + Mapping 'VX_alu_1_DW01_add_376' + Mapping 'VX_alu_1_DW01_add_377' + Mapping 'VX_alu_1_DW01_add_378' + Mapping 'VX_alu_1_DW01_add_379' + Mapping 'VX_alu_1_DW01_add_380' + Mapping 'VX_alu_1_DW01_add_381' + Mapping 'VX_alu_1_DW01_add_382' + Mapping 'VX_alu_1_DW01_add_383' + Mapping 'VX_alu_1_DW01_add_384' + Mapping 'VX_alu_1_DW01_add_385' + Mapping 'VX_alu_1_DW01_add_386' + Mapping 'VX_alu_1_DW01_add_387' + Mapping 'VX_alu_1_DW01_add_388' + Mapping 'VX_alu_1_DW01_add_389' + Mapping 'VX_alu_1_DW01_add_390' + Mapping 'VX_alu_1_DW01_add_391' + Mapping 'VX_alu_1_DW01_add_392' + Mapping 'VX_alu_1_DW01_add_393' + Mapping 'VX_alu_1_DW01_add_394' + Mapping 'VX_alu_1_DW01_add_395' + Mapping 'VX_alu_1_DW01_add_396' + Mapping 'VX_alu_1_DW01_add_397' + Mapping 'VX_alu_1_DW01_add_398' + Mapping 'VX_alu_1_DW01_add_399' + Mapping 'VX_alu_1_DW01_add_400' + Mapping 'VX_alu_1_DW01_add_401' + Mapping 'VX_alu_1_DW01_add_402' + Mapping 'VX_alu_1_DW01_add_403' + Mapping 'VX_alu_1_DW01_add_404' + Mapping 'VX_alu_1_DW01_add_405' + Mapping 'VX_alu_1_DW01_add_406' + Mapping 'VX_alu_1_DW01_add_407' + Mapping 'VX_alu_1_DW01_add_408' + Mapping 'VX_alu_1_DW01_add_409' + Mapping 'VX_alu_1_DW01_add_410' + Mapping 'VX_alu_1_DW01_add_411' + Mapping 'VX_alu_1_DW01_add_412' + Mapping 'VX_alu_1_DW01_add_413' + Mapping 'VX_alu_1_DW01_add_414' + Mapping 'VX_alu_1_DW01_add_415' + Mapping 'VX_alu_1_DW01_add_416' + Mapping 'VX_alu_1_DW01_add_417' + Mapping 'VX_alu_1_DW01_add_418' + Mapping 'VX_alu_1_DW01_add_419' + Mapping 'VX_alu_1_DW01_add_420' + Mapping 'VX_alu_1_DW01_add_421' + Mapping 'VX_alu_1_DW01_add_422' + Mapping 'VX_alu_1_DW01_add_423' + Mapping 'VX_alu_1_DW01_add_424' + Mapping 'VX_alu_1_DW01_add_425' + Mapping 'VX_alu_1_DW01_add_426' + Mapping 'VX_alu_1_DW01_add_427' + Mapping 'VX_alu_1_DW01_add_428' + Mapping 'VX_alu_1_DW01_add_429' + Mapping 'VX_alu_1_DW01_add_430' + Mapping 'VX_alu_1_DW01_add_431' + Mapping 'VX_alu_1_DW01_add_432' + Mapping 'VX_alu_1_DW01_add_433' + Mapping 'VX_alu_1_DW01_add_434' + Mapping 'VX_alu_1_DW01_add_435' + Mapping 'VX_alu_1_DW01_add_436' + Mapping 'VX_alu_1_DW01_add_437' + Mapping 'VX_alu_1_DW01_add_438' + Mapping 'VX_alu_1_DW01_add_439' + Mapping 'VX_alu_1_DW01_add_440' + Structuring 'VX_alu_2_DW_div_uns_3' + Mapping 'VX_alu_2_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_294' + Mapping 'VX_alu_2_DW01_add_295' + Mapping 'VX_alu_2_DW01_add_296' + Mapping 'VX_alu_2_DW01_add_297' + Mapping 'VX_alu_2_DW01_add_298' + Mapping 'VX_alu_2_DW01_add_299' + Mapping 'VX_alu_2_DW01_add_300' + Mapping 'VX_alu_2_DW01_add_301' + Mapping 'VX_alu_2_DW01_add_302' + Mapping 'VX_alu_2_DW01_add_303' + Mapping 'VX_alu_2_DW01_add_304' + Mapping 'VX_alu_2_DW01_add_305' + Mapping 'VX_alu_2_DW01_add_306' + Mapping 'VX_alu_2_DW01_add_307' + Mapping 'VX_alu_2_DW01_add_308' + Mapping 'VX_alu_2_DW01_add_309' + Mapping 'VX_alu_2_DW01_add_310' + Mapping 'VX_alu_2_DW01_add_311' + Mapping 'VX_alu_2_DW01_add_312' + Mapping 'VX_alu_2_DW01_add_313' + Mapping 'VX_alu_2_DW01_add_314' + Mapping 'VX_alu_2_DW01_add_315' + Mapping 'VX_alu_2_DW01_add_316' + Mapping 'VX_alu_2_DW01_add_317' + Mapping 'VX_alu_2_DW01_add_318' + Mapping 'VX_alu_2_DW01_add_319' + Mapping 'VX_alu_2_DW01_add_320' + Structuring 'VX_alu_2_DW_div_uns_4' + Mapping 'VX_alu_2_DW_div_uns_4' + Mapping 'VX_alu_2_DW01_add_321' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_322' + Mapping 'VX_alu_2_DW01_add_323' + Mapping 'VX_alu_2_DW01_add_324' + Mapping 'VX_alu_2_DW01_add_325' + Mapping 'VX_alu_2_DW01_add_326' + Mapping 'VX_alu_2_DW01_add_327' + Mapping 'VX_alu_2_DW01_add_328' + Mapping 'VX_alu_2_DW01_add_329' + Mapping 'VX_alu_2_DW01_add_330' + Mapping 'VX_alu_2_DW01_add_331' + Mapping 'VX_alu_2_DW01_add_332' + Mapping 'VX_alu_2_DW01_add_333' + Mapping 'VX_alu_2_DW01_add_334' + Mapping 'VX_alu_2_DW01_add_335' + Mapping 'VX_alu_2_DW01_add_336' + Mapping 'VX_alu_2_DW01_add_337' + Mapping 'VX_alu_2_DW01_add_338' + Mapping 'VX_alu_2_DW01_add_339' + Mapping 'VX_alu_2_DW01_add_340' + Mapping 'VX_alu_2_DW01_add_341' + Mapping 'VX_alu_2_DW01_add_342' + Mapping 'VX_alu_2_DW01_add_343' + Mapping 'VX_alu_2_DW01_add_344' + Mapping 'VX_alu_2_DW01_add_345' + Mapping 'VX_alu_2_DW01_add_346' + Mapping 'VX_alu_2_DW01_add_347' + Mapping 'VX_alu_2_DW01_add_348' + Mapping 'VX_alu_2_DW01_add_349' + Mapping 'VX_alu_2_DW01_add_350' + Mapping 'VX_alu_2_DW01_add_351' + Mapping 'VX_alu_2_DW01_add_352' + Mapping 'VX_alu_2_DW01_add_353' + Mapping 'VX_alu_2_DW01_add_354' + Mapping 'VX_alu_2_DW01_add_355' + Mapping 'VX_alu_2_DW01_add_356' + Mapping 'VX_alu_2_DW01_add_357' + Mapping 'VX_alu_2_DW01_add_358' + Mapping 'VX_alu_2_DW01_add_359' + Mapping 'VX_alu_2_DW01_add_360' + Structuring 'VX_alu_2_DW_div_uns_5' + Mapping 'VX_alu_2_DW_div_uns_5' + Mapping 'VX_alu_2_DW01_add_361' + Mapping 'VX_alu_2_DW01_add_362' + Mapping 'VX_alu_2_DW01_add_363' + Mapping 'VX_alu_2_DW01_sub_2' + Mapping 'VX_alu_2_DW01_add_364' + Mapping 'VX_alu_2_DW01_add_365' + Mapping 'VX_alu_2_DW01_add_366' + Mapping 'VX_alu_2_DW01_add_371' + Mapping 'VX_alu_2_DW01_add_372' + Mapping 'VX_alu_2_DW01_add_373' + Mapping 'VX_alu_2_DW01_add_374' + Mapping 'VX_alu_2_DW01_add_375' + Mapping 'VX_alu_2_DW01_add_376' + Mapping 'VX_alu_2_DW01_add_377' + Mapping 'VX_alu_2_DW01_add_378' + Mapping 'VX_alu_2_DW01_add_379' + Mapping 'VX_alu_2_DW01_add_380' + Mapping 'VX_alu_2_DW01_add_381' + Mapping 'VX_alu_2_DW01_add_382' + Mapping 'VX_alu_2_DW01_add_383' + Mapping 'VX_alu_2_DW01_add_384' + Mapping 'VX_alu_2_DW01_add_385' + Mapping 'VX_alu_2_DW01_add_386' + Mapping 'VX_alu_2_DW01_add_387' + Mapping 'VX_alu_2_DW01_add_388' + Mapping 'VX_alu_2_DW01_add_389' + Mapping 'VX_alu_2_DW01_add_390' + Mapping 'VX_alu_2_DW01_add_391' + Mapping 'VX_alu_2_DW01_add_392' + Mapping 'VX_alu_2_DW01_add_393' + Mapping 'VX_alu_2_DW01_add_394' + Mapping 'VX_alu_2_DW01_add_395' + Mapping 'VX_alu_2_DW01_add_396' + Mapping 'VX_alu_2_DW01_add_397' + Mapping 'VX_alu_2_DW01_add_398' + Mapping 'VX_alu_2_DW01_add_399' + Mapping 'VX_alu_2_DW01_add_400' + Mapping 'VX_alu_2_DW01_add_401' + Mapping 'VX_alu_2_DW01_add_402' + Mapping 'VX_alu_2_DW01_add_403' + Mapping 'VX_alu_2_DW01_add_404' + Mapping 'VX_alu_2_DW01_add_405' + Mapping 'VX_alu_2_DW01_add_406' + Mapping 'VX_alu_2_DW01_add_407' + Mapping 'VX_alu_2_DW01_add_408' + Mapping 'VX_alu_2_DW01_add_409' + Mapping 'VX_alu_2_DW01_add_410' + Mapping 'VX_alu_2_DW01_add_411' + Mapping 'VX_alu_2_DW01_add_412' + Mapping 'VX_alu_2_DW01_add_413' + Mapping 'VX_alu_2_DW01_add_414' + Mapping 'VX_alu_2_DW01_add_415' + Mapping 'VX_alu_2_DW01_add_416' + Mapping 'VX_alu_2_DW01_add_417' + Mapping 'VX_alu_2_DW01_add_418' + Mapping 'VX_alu_2_DW01_add_419' + Mapping 'VX_alu_2_DW01_add_420' + Mapping 'VX_alu_2_DW01_add_421' + Mapping 'VX_alu_2_DW01_add_422' + Mapping 'VX_alu_2_DW01_add_423' + Mapping 'VX_alu_2_DW01_add_424' + Mapping 'VX_alu_2_DW01_add_425' + Mapping 'VX_alu_2_DW01_add_426' + Mapping 'VX_alu_2_DW01_add_427' + Mapping 'VX_alu_2_DW01_add_428' + Mapping 'VX_alu_2_DW01_add_429' + Mapping 'VX_alu_2_DW01_add_430' + Mapping 'VX_alu_2_DW01_add_431' + Mapping 'VX_alu_2_DW01_add_432' + Mapping 'VX_alu_2_DW01_add_433' + Mapping 'VX_alu_2_DW01_add_434' + Mapping 'VX_alu_2_DW01_add_435' + Mapping 'VX_alu_2_DW01_add_436' + Mapping 'VX_alu_2_DW01_add_437' + Mapping 'VX_alu_2_DW01_add_438' + Mapping 'VX_alu_2_DW01_add_439' + Mapping 'VX_alu_2_DW01_add_440' + Structuring 'VX_alu_0_DW_div_tc_3' + Mapping 'VX_alu_0_DW_div_tc_3' + Structuring 'VX_alu_0_DW01_absval_3' + Mapping 'VX_alu_0_DW01_absval_3' + Structuring 'VX_alu_0_DW01_inc_3' + Mapping 'VX_alu_0_DW01_inc_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_441' + Mapping 'VX_alu_0_DW01_add_442' + Mapping 'VX_alu_0_DW01_add_443' + Mapping 'VX_alu_0_DW01_add_444' + Mapping 'VX_alu_0_DW01_add_445' + Mapping 'VX_alu_0_DW01_add_446' + Mapping 'VX_alu_0_DW01_add_447' + Mapping 'VX_alu_0_DW01_add_448' + Mapping 'VX_alu_0_DW01_add_449' + Mapping 'VX_alu_0_DW01_add_450' + Mapping 'VX_alu_0_DW01_add_451' + Mapping 'VX_alu_0_DW01_add_452' + Mapping 'VX_alu_0_DW01_add_453' + Mapping 'VX_alu_0_DW01_add_454' + Mapping 'VX_alu_0_DW01_add_455' + Mapping 'VX_alu_0_DW01_add_456' + Mapping 'VX_alu_0_DW01_add_457' + Mapping 'VX_alu_0_DW01_add_458' + Mapping 'VX_alu_0_DW01_add_459' + Mapping 'VX_alu_0_DW01_add_460' + Mapping 'VX_alu_0_DW01_add_461' + Mapping 'VX_alu_0_DW01_add_462' + Mapping 'VX_alu_0_DW01_add_463' + Mapping 'VX_alu_0_DW01_add_464' + Mapping 'VX_alu_0_DW01_add_465' + Mapping 'VX_alu_0_DW01_add_466' + Mapping 'VX_alu_0_DW01_add_467' + Mapping 'VX_alu_0_DW_inc_6' + Structuring 'VX_alu_0_DW_div_tc_4' + Mapping 'VX_alu_0_DW_div_tc_4' + Structuring 'VX_alu_0_DW01_absval_4' + Mapping 'VX_alu_0_DW01_absval_4' + Structuring 'VX_alu_0_DW01_inc_4' + Mapping 'VX_alu_0_DW01_inc_4' + Mapping 'VX_alu_0_DW01_add_468' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_469' + Mapping 'VX_alu_0_DW01_add_470' + Mapping 'VX_alu_0_DW01_add_471' + Mapping 'VX_alu_0_DW01_add_472' + Mapping 'VX_alu_0_DW01_add_473' + Mapping 'VX_alu_0_DW01_add_474' + Mapping 'VX_alu_0_DW01_add_475' + Mapping 'VX_alu_0_DW01_add_476' + Mapping 'VX_alu_0_DW01_add_477' + Mapping 'VX_alu_0_DW01_add_478' + Mapping 'VX_alu_0_DW01_add_479' + Mapping 'VX_alu_0_DW01_add_480' + Mapping 'VX_alu_0_DW01_add_481' + Mapping 'VX_alu_0_DW01_add_482' + Mapping 'VX_alu_0_DW01_add_483' + Mapping 'VX_alu_0_DW01_add_484' + Mapping 'VX_alu_0_DW01_add_485' + Mapping 'VX_alu_0_DW01_add_486' + Mapping 'VX_alu_0_DW01_add_487' + Mapping 'VX_alu_0_DW01_add_488' + Mapping 'VX_alu_0_DW01_add_489' + Mapping 'VX_alu_0_DW01_add_490' + Mapping 'VX_alu_0_DW01_add_491' + Mapping 'VX_alu_0_DW01_add_492' + Mapping 'VX_alu_0_DW01_add_493' + Mapping 'VX_alu_0_DW01_add_494' + Mapping 'VX_alu_0_DW01_add_495' + Mapping 'VX_alu_0_DW01_add_496' + Mapping 'VX_alu_0_DW01_add_497' + Mapping 'VX_alu_0_DW01_add_498' + Mapping 'VX_alu_0_DW01_add_499' + Mapping 'VX_alu_0_DW01_add_500' + Mapping 'VX_alu_0_DW01_add_501' + Mapping 'VX_alu_0_DW01_add_502' + Mapping 'VX_alu_0_DW01_add_503' + Mapping 'VX_alu_0_DW01_add_504' + Mapping 'VX_alu_0_DW01_add_505' + Mapping 'VX_alu_0_DW01_add_506' + Mapping 'VX_alu_0_DW01_add_507' + Mapping 'VX_alu_0_DW_inc_8' + Structuring 'VX_alu_0_DW_div_tc_5' + Mapping 'VX_alu_0_DW_div_tc_5' + Structuring 'VX_alu_0_DW01_absval_5' + Mapping 'VX_alu_0_DW01_absval_5' + Structuring 'VX_alu_0_DW01_inc_5' + Mapping 'VX_alu_0_DW01_inc_5' + Mapping 'VX_alu_0_DW01_add_508' + Mapping 'VX_alu_0_DW01_add_509' + Mapping 'VX_alu_0_DW01_add_510' + Mapping 'VX_alu_0_DW01_sub_3' + Mapping 'VX_alu_0_DW01_add_511' + Mapping 'VX_alu_0_DW01_add_512' + Mapping 'VX_alu_0_DW01_add_513' + Mapping 'VX_alu_0_DW01_add_518' + Mapping 'VX_alu_0_DW01_add_519' + Mapping 'VX_alu_0_DW01_add_520' + Mapping 'VX_alu_0_DW01_add_521' + Mapping 'VX_alu_0_DW01_add_522' + Mapping 'VX_alu_0_DW01_add_523' + Mapping 'VX_alu_0_DW01_add_524' + Mapping 'VX_alu_0_DW01_add_525' + Mapping 'VX_alu_0_DW01_add_526' + Mapping 'VX_alu_0_DW01_add_527' + Mapping 'VX_alu_0_DW01_add_528' + Mapping 'VX_alu_0_DW01_add_529' + Mapping 'VX_alu_0_DW01_add_530' + Mapping 'VX_alu_0_DW01_add_531' + Mapping 'VX_alu_0_DW01_add_532' + Mapping 'VX_alu_0_DW01_add_533' + Mapping 'VX_alu_0_DW01_add_534' + Mapping 'VX_alu_0_DW01_add_535' + Mapping 'VX_alu_0_DW01_add_536' + Mapping 'VX_alu_0_DW01_add_537' + Mapping 'VX_alu_0_DW01_add_538' + Mapping 'VX_alu_0_DW01_add_539' + Mapping 'VX_alu_0_DW01_add_540' + Mapping 'VX_alu_0_DW01_add_541' + Mapping 'VX_alu_0_DW01_add_542' + Mapping 'VX_alu_0_DW01_add_543' + Mapping 'VX_alu_0_DW01_add_544' + Mapping 'VX_alu_0_DW01_add_545' + Mapping 'VX_alu_0_DW01_add_546' + Mapping 'VX_alu_0_DW01_add_547' + Mapping 'VX_alu_0_DW01_add_548' + Mapping 'VX_alu_0_DW01_add_549' + Mapping 'VX_alu_0_DW01_add_550' + Mapping 'VX_alu_0_DW01_add_551' + Mapping 'VX_alu_0_DW01_add_552' + Mapping 'VX_alu_0_DW01_add_553' + Mapping 'VX_alu_0_DW01_add_554' + Mapping 'VX_alu_0_DW01_add_555' + Mapping 'VX_alu_0_DW01_add_556' + Mapping 'VX_alu_0_DW01_add_557' + Mapping 'VX_alu_0_DW01_add_558' + Mapping 'VX_alu_0_DW01_add_559' + Mapping 'VX_alu_0_DW01_add_560' + Mapping 'VX_alu_0_DW01_add_561' + Mapping 'VX_alu_0_DW01_add_562' + Mapping 'VX_alu_0_DW01_add_563' + Mapping 'VX_alu_0_DW01_add_564' + Mapping 'VX_alu_0_DW01_add_565' + Mapping 'VX_alu_0_DW01_add_566' + Mapping 'VX_alu_0_DW01_add_567' + Mapping 'VX_alu_0_DW01_add_568' + Mapping 'VX_alu_0_DW01_add_569' + Mapping 'VX_alu_0_DW01_add_570' + Mapping 'VX_alu_0_DW01_add_571' + Mapping 'VX_alu_0_DW01_add_572' + Mapping 'VX_alu_0_DW01_add_573' + Mapping 'VX_alu_0_DW01_add_574' + Mapping 'VX_alu_0_DW01_add_575' + Mapping 'VX_alu_0_DW01_add_576' + Mapping 'VX_alu_0_DW01_add_577' + Mapping 'VX_alu_0_DW01_add_578' + Mapping 'VX_alu_0_DW01_add_579' + Mapping 'VX_alu_0_DW01_add_580' + Mapping 'VX_alu_0_DW01_add_581' + Mapping 'VX_alu_0_DW01_add_582' + Mapping 'VX_alu_0_DW01_add_583' + Mapping 'VX_alu_0_DW01_add_584' + Mapping 'VX_alu_0_DW01_add_585' + Mapping 'VX_alu_0_DW01_add_586' + Mapping 'VX_alu_0_DW01_add_587' + Mapping 'VX_alu_0_DW_inc_10' + Structuring 'VX_alu_1_DW_div_tc_3' + Mapping 'VX_alu_1_DW_div_tc_3' + Structuring 'VX_alu_1_DW01_absval_3' + Mapping 'VX_alu_1_DW01_absval_3' + Structuring 'VX_alu_1_DW01_inc_3' + Mapping 'VX_alu_1_DW01_inc_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_441' + Mapping 'VX_alu_1_DW01_add_442' + Mapping 'VX_alu_1_DW01_add_443' + Mapping 'VX_alu_1_DW01_add_444' + Mapping 'VX_alu_1_DW01_add_445' + Mapping 'VX_alu_1_DW01_add_446' + Mapping 'VX_alu_1_DW01_add_447' + Mapping 'VX_alu_1_DW01_add_448' + Mapping 'VX_alu_1_DW01_add_449' + Mapping 'VX_alu_1_DW01_add_450' + Mapping 'VX_alu_1_DW01_add_451' + Mapping 'VX_alu_1_DW01_add_452' + Mapping 'VX_alu_1_DW01_add_453' + Mapping 'VX_alu_1_DW01_add_454' + Mapping 'VX_alu_1_DW01_add_455' + Mapping 'VX_alu_1_DW01_add_456' + Mapping 'VX_alu_1_DW01_add_457' + Mapping 'VX_alu_1_DW01_add_458' + Mapping 'VX_alu_1_DW01_add_459' + Mapping 'VX_alu_1_DW01_add_460' + Mapping 'VX_alu_1_DW01_add_461' + Mapping 'VX_alu_1_DW01_add_462' + Mapping 'VX_alu_1_DW01_add_463' + Mapping 'VX_alu_1_DW01_add_464' + Mapping 'VX_alu_1_DW01_add_465' + Mapping 'VX_alu_1_DW01_add_466' + Mapping 'VX_alu_1_DW01_add_467' + Mapping 'VX_alu_1_DW_inc_6' + Structuring 'VX_alu_1_DW_div_tc_4' + Mapping 'VX_alu_1_DW_div_tc_4' + Structuring 'VX_alu_1_DW01_absval_4' + Mapping 'VX_alu_1_DW01_absval_4' + Structuring 'VX_alu_1_DW01_inc_4' + Mapping 'VX_alu_1_DW01_inc_4' + Mapping 'VX_alu_1_DW01_add_468' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_469' + Mapping 'VX_alu_1_DW01_add_470' + Mapping 'VX_alu_1_DW01_add_471' + Mapping 'VX_alu_1_DW01_add_472' + Mapping 'VX_alu_1_DW01_add_473' + Mapping 'VX_alu_1_DW01_add_474' + Mapping 'VX_alu_1_DW01_add_475' + Mapping 'VX_alu_1_DW01_add_476' + Mapping 'VX_alu_1_DW01_add_477' + Mapping 'VX_alu_1_DW01_add_478' + Mapping 'VX_alu_1_DW01_add_479' + Mapping 'VX_alu_1_DW01_add_480' + Mapping 'VX_alu_1_DW01_add_481' + Mapping 'VX_alu_1_DW01_add_482' + Mapping 'VX_alu_1_DW01_add_483' + Mapping 'VX_alu_1_DW01_add_484' + Mapping 'VX_alu_1_DW01_add_485' + Mapping 'VX_alu_1_DW01_add_486' + Mapping 'VX_alu_1_DW01_add_487' + Mapping 'VX_alu_1_DW01_add_488' + Mapping 'VX_alu_1_DW01_add_489' + Mapping 'VX_alu_1_DW01_add_490' + Mapping 'VX_alu_1_DW01_add_491' + Mapping 'VX_alu_1_DW01_add_492' + Mapping 'VX_alu_1_DW01_add_493' + Mapping 'VX_alu_1_DW01_add_494' + Mapping 'VX_alu_1_DW01_add_495' + Mapping 'VX_alu_1_DW01_add_496' + Mapping 'VX_alu_1_DW01_add_497' + Mapping 'VX_alu_1_DW01_add_498' + Mapping 'VX_alu_1_DW01_add_499' + Mapping 'VX_alu_1_DW01_add_500' + Mapping 'VX_alu_1_DW01_add_501' + Mapping 'VX_alu_1_DW01_add_502' + Mapping 'VX_alu_1_DW01_add_503' + Mapping 'VX_alu_1_DW01_add_504' + Mapping 'VX_alu_1_DW01_add_505' + Mapping 'VX_alu_1_DW01_add_506' + Mapping 'VX_alu_1_DW01_add_507' + Mapping 'VX_alu_1_DW_inc_8' + Structuring 'VX_alu_1_DW_div_tc_5' + Mapping 'VX_alu_1_DW_div_tc_5' + Structuring 'VX_alu_1_DW01_absval_5' + Mapping 'VX_alu_1_DW01_absval_5' + Structuring 'VX_alu_1_DW01_inc_5' + Mapping 'VX_alu_1_DW01_inc_5' + Mapping 'VX_alu_1_DW01_add_508' + Mapping 'VX_alu_1_DW01_add_509' + Mapping 'VX_alu_1_DW01_add_510' + Mapping 'VX_alu_1_DW01_sub_3' + Mapping 'VX_alu_1_DW01_add_511' + Mapping 'VX_alu_1_DW01_add_512' + Mapping 'VX_alu_1_DW01_add_513' + Mapping 'VX_alu_1_DW01_add_518' + Mapping 'VX_alu_1_DW01_add_519' + Mapping 'VX_alu_1_DW01_add_520' + Mapping 'VX_alu_1_DW01_add_521' + Mapping 'VX_alu_1_DW01_add_522' + Mapping 'VX_alu_1_DW01_add_523' + Mapping 'VX_alu_1_DW01_add_524' + Mapping 'VX_alu_1_DW01_add_525' + Mapping 'VX_alu_1_DW01_add_526' + Mapping 'VX_alu_1_DW01_add_527' + Mapping 'VX_alu_1_DW01_add_528' + Mapping 'VX_alu_1_DW01_add_529' + Mapping 'VX_alu_1_DW01_add_530' + Mapping 'VX_alu_1_DW01_add_531' + Mapping 'VX_alu_1_DW01_add_532' + Mapping 'VX_alu_1_DW01_add_533' + Mapping 'VX_alu_1_DW01_add_534' + Mapping 'VX_alu_1_DW01_add_535' + Mapping 'VX_alu_1_DW01_add_536' + Mapping 'VX_alu_1_DW01_add_537' + Mapping 'VX_alu_1_DW01_add_538' + Mapping 'VX_alu_1_DW01_add_539' + Mapping 'VX_alu_1_DW01_add_540' + Mapping 'VX_alu_1_DW01_add_541' + Mapping 'VX_alu_1_DW01_add_542' + Mapping 'VX_alu_1_DW01_add_543' + Mapping 'VX_alu_1_DW01_add_544' + Mapping 'VX_alu_1_DW01_add_545' + Mapping 'VX_alu_1_DW01_add_546' + Mapping 'VX_alu_1_DW01_add_547' + Mapping 'VX_alu_1_DW01_add_548' + Mapping 'VX_alu_1_DW01_add_549' + Mapping 'VX_alu_1_DW01_add_550' + Mapping 'VX_alu_1_DW01_add_551' + Mapping 'VX_alu_1_DW01_add_552' + Mapping 'VX_alu_1_DW01_add_553' + Mapping 'VX_alu_1_DW01_add_554' + Mapping 'VX_alu_1_DW01_add_555' + Mapping 'VX_alu_1_DW01_add_556' + Mapping 'VX_alu_1_DW01_add_557' + Mapping 'VX_alu_1_DW01_add_558' + Mapping 'VX_alu_1_DW01_add_559' + Mapping 'VX_alu_1_DW01_add_560' + Mapping 'VX_alu_1_DW01_add_561' + Mapping 'VX_alu_1_DW01_add_562' + Mapping 'VX_alu_1_DW01_add_563' + Mapping 'VX_alu_1_DW01_add_564' + Mapping 'VX_alu_1_DW01_add_565' + Mapping 'VX_alu_1_DW01_add_566' + Mapping 'VX_alu_1_DW01_add_567' + Mapping 'VX_alu_1_DW01_add_568' + Mapping 'VX_alu_1_DW01_add_569' + Mapping 'VX_alu_1_DW01_add_570' + Mapping 'VX_alu_1_DW01_add_571' + Mapping 'VX_alu_1_DW01_add_572' + Mapping 'VX_alu_1_DW01_add_573' + Mapping 'VX_alu_1_DW01_add_574' + Mapping 'VX_alu_1_DW01_add_575' + Mapping 'VX_alu_1_DW01_add_576' + Mapping 'VX_alu_1_DW01_add_577' + Mapping 'VX_alu_1_DW01_add_578' + Mapping 'VX_alu_1_DW01_add_579' + Mapping 'VX_alu_1_DW01_add_580' + Mapping 'VX_alu_1_DW01_add_581' + Mapping 'VX_alu_1_DW01_add_582' + Mapping 'VX_alu_1_DW01_add_583' + Mapping 'VX_alu_1_DW01_add_584' + Mapping 'VX_alu_1_DW01_add_585' + Mapping 'VX_alu_1_DW01_add_586' + Mapping 'VX_alu_1_DW01_add_587' + Mapping 'VX_alu_1_DW_inc_10' + Structuring 'VX_alu_2_DW_div_tc_3' + Mapping 'VX_alu_2_DW_div_tc_3' + Structuring 'VX_alu_2_DW01_absval_3' + Mapping 'VX_alu_2_DW01_absval_3' + Structuring 'VX_alu_2_DW01_inc_3' + Mapping 'VX_alu_2_DW01_inc_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_441' + Mapping 'VX_alu_2_DW01_add_442' + Mapping 'VX_alu_2_DW01_add_443' + Mapping 'VX_alu_2_DW01_add_444' + Mapping 'VX_alu_2_DW01_add_445' + Mapping 'VX_alu_2_DW01_add_446' + Mapping 'VX_alu_2_DW01_add_447' + Mapping 'VX_alu_2_DW01_add_448' + Mapping 'VX_alu_2_DW01_add_449' + Mapping 'VX_alu_2_DW01_add_450' + Mapping 'VX_alu_2_DW01_add_451' + Mapping 'VX_alu_2_DW01_add_452' + Mapping 'VX_alu_2_DW01_add_453' + Mapping 'VX_alu_2_DW01_add_454' + Mapping 'VX_alu_2_DW01_add_455' + Mapping 'VX_alu_2_DW01_add_456' + Mapping 'VX_alu_2_DW01_add_457' + Mapping 'VX_alu_2_DW01_add_458' + Mapping 'VX_alu_2_DW01_add_459' + Mapping 'VX_alu_2_DW01_add_460' + Mapping 'VX_alu_2_DW01_add_461' + Mapping 'VX_alu_2_DW01_add_462' + Mapping 'VX_alu_2_DW01_add_463' + Mapping 'VX_alu_2_DW01_add_464' + Mapping 'VX_alu_2_DW01_add_465' + Mapping 'VX_alu_2_DW01_add_466' + Mapping 'VX_alu_2_DW01_add_467' + Mapping 'VX_alu_2_DW_inc_6' + Structuring 'VX_alu_2_DW_div_tc_4' + Mapping 'VX_alu_2_DW_div_tc_4' + Structuring 'VX_alu_2_DW01_absval_4' + Mapping 'VX_alu_2_DW01_absval_4' + Structuring 'VX_alu_2_DW01_inc_4' + Mapping 'VX_alu_2_DW01_inc_4' + Mapping 'VX_alu_2_DW01_add_468' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_469' + Mapping 'VX_alu_2_DW01_add_470' + Mapping 'VX_alu_2_DW01_add_471' + Mapping 'VX_alu_2_DW01_add_472' + Mapping 'VX_alu_2_DW01_add_473' + Mapping 'VX_alu_2_DW01_add_474' + Mapping 'VX_alu_2_DW01_add_475' + Mapping 'VX_alu_2_DW01_add_476' + Mapping 'VX_alu_2_DW01_add_477' + Mapping 'VX_alu_2_DW01_add_478' + Mapping 'VX_alu_2_DW01_add_479' + Mapping 'VX_alu_2_DW01_add_480' + Mapping 'VX_alu_2_DW01_add_481' + Mapping 'VX_alu_2_DW01_add_482' + Mapping 'VX_alu_2_DW01_add_483' + Mapping 'VX_alu_2_DW01_add_484' + Mapping 'VX_alu_2_DW01_add_485' + Mapping 'VX_alu_2_DW01_add_486' + Mapping 'VX_alu_2_DW01_add_487' + Mapping 'VX_alu_2_DW01_add_488' + Mapping 'VX_alu_2_DW01_add_489' + Mapping 'VX_alu_2_DW01_add_490' + Mapping 'VX_alu_2_DW01_add_491' + Mapping 'VX_alu_2_DW01_add_492' + Mapping 'VX_alu_2_DW01_add_493' + Mapping 'VX_alu_2_DW01_add_494' + Mapping 'VX_alu_2_DW01_add_495' + Mapping 'VX_alu_2_DW01_add_496' + Mapping 'VX_alu_2_DW01_add_497' + Mapping 'VX_alu_2_DW01_add_498' + Mapping 'VX_alu_2_DW01_add_499' + Mapping 'VX_alu_2_DW01_add_500' + Mapping 'VX_alu_2_DW01_add_501' + Mapping 'VX_alu_2_DW01_add_502' + Mapping 'VX_alu_2_DW01_add_503' + Mapping 'VX_alu_2_DW01_add_504' + Mapping 'VX_alu_2_DW01_add_505' + Mapping 'VX_alu_2_DW01_add_506' + Mapping 'VX_alu_2_DW01_add_507' + Mapping 'VX_alu_2_DW_inc_8' + Structuring 'VX_alu_2_DW_div_tc_5' + Mapping 'VX_alu_2_DW_div_tc_5' + Structuring 'VX_alu_2_DW01_absval_5' + Mapping 'VX_alu_2_DW01_absval_5' + Structuring 'VX_alu_2_DW01_inc_5' + Mapping 'VX_alu_2_DW01_inc_5' + Mapping 'VX_alu_2_DW01_add_508' + Mapping 'VX_alu_2_DW01_add_509' + Mapping 'VX_alu_2_DW01_add_510' + Mapping 'VX_alu_2_DW01_sub_3' + Mapping 'VX_alu_2_DW01_add_511' + Mapping 'VX_alu_2_DW01_add_512' + Mapping 'VX_alu_2_DW01_add_513' + Mapping 'VX_alu_2_DW01_add_518' + Mapping 'VX_alu_2_DW01_add_519' + Mapping 'VX_alu_2_DW01_add_520' + Mapping 'VX_alu_2_DW01_add_521' + Mapping 'VX_alu_2_DW01_add_522' + Mapping 'VX_alu_2_DW01_add_523' + Mapping 'VX_alu_2_DW01_add_524' + Mapping 'VX_alu_2_DW01_add_525' + Mapping 'VX_alu_2_DW01_add_526' + Mapping 'VX_alu_2_DW01_add_527' + Mapping 'VX_alu_2_DW01_add_528' + Mapping 'VX_alu_2_DW01_add_529' + Mapping 'VX_alu_2_DW01_add_530' + Mapping 'VX_alu_2_DW01_add_531' + Mapping 'VX_alu_2_DW01_add_532' + Mapping 'VX_alu_2_DW01_add_533' + Mapping 'VX_alu_2_DW01_add_534' + Mapping 'VX_alu_2_DW01_add_535' + Mapping 'VX_alu_2_DW01_add_536' + Mapping 'VX_alu_2_DW01_add_537' + Mapping 'VX_alu_2_DW01_add_538' + Mapping 'VX_alu_2_DW01_add_539' + Mapping 'VX_alu_2_DW01_add_540' + Mapping 'VX_alu_2_DW01_add_541' + Mapping 'VX_alu_2_DW01_add_542' + Mapping 'VX_alu_2_DW01_add_543' + Mapping 'VX_alu_2_DW01_add_544' + Mapping 'VX_alu_2_DW01_add_545' + Mapping 'VX_alu_2_DW01_add_546' + Mapping 'VX_alu_2_DW01_add_547' + Mapping 'VX_alu_2_DW01_add_548' + Mapping 'VX_alu_2_DW01_add_549' + Mapping 'VX_alu_2_DW01_add_550' + Mapping 'VX_alu_2_DW01_add_551' + Mapping 'VX_alu_2_DW01_add_552' + Mapping 'VX_alu_2_DW01_add_553' + Mapping 'VX_alu_2_DW01_add_554' + Mapping 'VX_alu_2_DW01_add_555' + Mapping 'VX_alu_2_DW01_add_556' + Mapping 'VX_alu_2_DW01_add_557' + Mapping 'VX_alu_2_DW01_add_558' + Mapping 'VX_alu_2_DW01_add_559' + Mapping 'VX_alu_2_DW01_add_560' + Mapping 'VX_alu_2_DW01_add_561' + Mapping 'VX_alu_2_DW01_add_562' + Mapping 'VX_alu_2_DW01_add_563' + Mapping 'VX_alu_2_DW01_add_564' + Mapping 'VX_alu_2_DW01_add_565' + Mapping 'VX_alu_2_DW01_add_566' + Mapping 'VX_alu_2_DW01_add_567' + Mapping 'VX_alu_2_DW01_add_568' + Mapping 'VX_alu_2_DW01_add_569' + Mapping 'VX_alu_2_DW01_add_570' + Mapping 'VX_alu_2_DW01_add_571' + Mapping 'VX_alu_2_DW01_add_572' + Mapping 'VX_alu_2_DW01_add_573' + Mapping 'VX_alu_2_DW01_add_574' + Mapping 'VX_alu_2_DW01_add_575' + Mapping 'VX_alu_2_DW01_add_576' + Mapping 'VX_alu_2_DW01_add_577' + Mapping 'VX_alu_2_DW01_add_578' + Mapping 'VX_alu_2_DW01_add_579' + Mapping 'VX_alu_2_DW01_add_580' + Mapping 'VX_alu_2_DW01_add_581' + Mapping 'VX_alu_2_DW01_add_582' + Mapping 'VX_alu_2_DW01_add_583' + Mapping 'VX_alu_2_DW01_add_584' + Mapping 'VX_alu_2_DW01_add_585' + Mapping 'VX_alu_2_DW01_add_586' + Mapping 'VX_alu_2_DW01_add_587' + Mapping 'VX_alu_2_DW_inc_10' + Mapping Optimization (Phase 1) + Mapping Optimization (Phase 2) +Information: Added key list 'DesignWare' to design 'VX_lsu_addr_gen'. (DDB-72) + + Beginning Constant Register Removal + ----------------------------------- + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 0:16:11 804749.2 0.00 0.0 0.8 115.1815 + 0:16:11 804749.2 0.00 0.0 0.8 115.1815 + 0:16:13 805677.8 0.00 0.0 0.8 115.5818 + + Beginning Global Optimizations + ------------------------------ + Numerical Synthesis (Phase 1) + Numerical Synthesis (Phase 2) + Global Optimization (Phase 1) + Global Optimization (Phase 2) + Global Optimization (Phase 3) + Global Optimization (Phase 4) + Global Optimization (Phase 5) + Global Optimization (Phase 6) + Global Optimization (Phase 7) + Global Optimization (Phase 8) + Global Optimization (Phase 9) + Global Optimization (Phase 10) + Global Optimization (Phase 11) + Global Optimization (Phase 12) + Global Optimization (Phase 13) + Global Optimization (Phase 14) + Global Optimization (Phase 15) + Global Optimization (Phase 16) + Global Optimization (Phase 17) + Global Optimization (Phase 18) + Global Optimization (Phase 19) + Global Optimization (Phase 20) + Global Optimization (Phase 21) + Global Optimization (Phase 22) + Global Optimization (Phase 23) + Global Optimization (Phase 24) + Global Optimization (Phase 25) + Global Optimization (Phase 26) + Global Optimization (Phase 27) + Global Optimization (Phase 28) + Global Optimization (Phase 29) + Global Optimization (Phase 30) + Global Optimization (Phase 31) + Global Optimization (Phase 32) + Mapping 'VX_alu_3_DW01_add_692' + Mapping 'VX_alu_3_DW01_add_693' + Mapping 'VX_alu_3_DW01_add_694' + Mapping 'VX_alu_3_DW01_add_695' + Mapping 'VX_alu_3_DW01_add_696' + Mapping 'VX_alu_3_DW01_add_697' + Mapping 'VX_alu_3_DW01_add_698' + Mapping 'VX_alu_3_DW01_add_699' + Mapping 'VX_alu_3_DW01_add_700' + Mapping 'VX_alu_3_DW01_add_701' + Mapping 'VX_alu_3_DW01_add_702' + Mapping 'VX_alu_3_DW01_add_703' + Mapping 'VX_alu_3_DW01_add_704' + Mapping 'VX_alu_3_DW01_add_705' + Mapping 'VX_alu_3_DW01_add_706' + Mapping 'VX_alu_3_DW01_add_707' + Mapping 'VX_alu_3_DW01_add_708' + Mapping 'VX_alu_3_DW01_add_709' + Mapping 'VX_alu_3_DW01_add_710' + Mapping 'VX_alu_3_DW01_add_711' + Mapping 'VX_alu_3_DW01_add_712' + + Beginning Isolate Ports + ----------------------- + + Beginning Delay Optimization + ---------------------------- + 0:18:08 612551.3 4.21 6011.1 10.2 55.4856 + 0:21:23 621013.4 0.49 555.2 11.4 58.1080 + 0:21:23 621013.4 0.49 555.2 11.4 58.1080 + 0:21:26 621038.8 0.49 561.3 11.4 58.1127 + + Beginning WLM Backend Optimization + -------------------------------------- + 0:25:47 620167.1 0.73 1023.3 11.1 57.9233 + 0:25:58 620080.4 0.73 1048.6 10.9 57.8820 + 0:26:08 620009.1 0.73 1045.8 10.8 57.8456 + 0:26:12 619924.4 0.72 1041.2 10.7 57.8103 + 0:26:17 619780.1 0.68 966.9 10.6 57.7746 + 0:26:52 619561.8 0.68 1028.0 10.5 57.7272 + 0:27:04 619327.6 0.68 1025.9 10.4 57.6812 + 0:27:08 619182.4 0.68 1026.4 10.3 57.6542 + 0:27:15 619048.3 0.68 1023.7 10.3 57.6318 + 0:27:18 618909.6 0.68 1019.8 10.3 57.6051 + 0:27:27 618892.1 0.65 959.4 10.5 57.6161 + 0:28:09 619828.0 0.50 643.9 11.3 57.9211 + 0:28:51 620713.0 0.42 477.7 11.6 58.1995 + 0:29:29 621512.7 0.37 347.9 12.1 58.4525 + 0:30:06 622210.1 0.32 233.0 12.5 58.6699 + 0:30:47 622876.0 0.27 131.3 13.0 58.8794 + 0:31:10 623160.4 0.25 96.2 13.2 58.9671 + 0:31:12 623192.3 0.25 95.8 13.2 58.9750 + 0:33:15 622441.6 0.21 56.9 5.5 57.5180 + 0:33:16 622441.6 0.21 56.9 5.5 57.5180 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:25 625136.3 0.00 0.0 6.4 58.3560 + 0:34:26 625136.3 0.00 0.0 6.4 58.3560 + 0:34:26 625136.3 0.00 0.0 6.4 58.3560 + 0:34:26 625136.3 0.00 0.0 6.4 58.3560 + 0:34:26 625136.3 0.00 0.0 6.4 58.3560 + + + Beginning Design Rule Fixing (max_transition) (max_capacitance) + ---------------------------- + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 0:34:26 625136.3 0.00 0.0 6.4 58.3560 + Global Optimization (Phase 33) + Global Optimization (Phase 34) + Global Optimization (Phase 35) + 0:34:34 625011.5 0.00 0.0 0.0 58.3147 + 0:34:34 625011.5 0.00 0.0 0.0 58.3147 + + + Beginning Leakage Power Optimization (max_leakage_power 0) + ------------------------------------ + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 0:34:34 625011.5 0.00 0.0 0.0 58.3147 + Global Optimization (Phase 36) + Global Optimization (Phase 37) + Global Optimization (Phase 38) + Global Optimization (Phase 39) + Global Optimization (Phase 40) + Global Optimization (Phase 41) + Global Optimization (Phase 42) + Global Optimization (Phase 43) + Global Optimization (Phase 44) + Global Optimization (Phase 45) + Global Optimization (Phase 46) + Global Optimization (Phase 47) + Global Optimization (Phase 48) + Global Optimization (Phase 49) + Global Optimization (Phase 50) + Global Optimization (Phase 51) + Global Optimization (Phase 52) + Global Optimization (Phase 53) + 0:35:27 615217.8 4.46 9197.7 0.0 55.4689 +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_3'. + The new name of the port is 'reset_BAR'. (OPT-319) +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_4'. + The new name of the port is 'reset_BAR'. (OPT-319) +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_5'. + The new name of the port is 'reset_BAR'. (OPT-319) +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_1'. + The new name of the port is 'reset_BAR'. (OPT-319) +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_2'. + The new name of the port is 'reset_BAR'. (OPT-319) +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_7'. + The new name of the port is 'reset_BAR'. (OPT-319) + 0:36:07 615863.2 2.05 3899.1 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[7][24]/D 55.6599 + 0:36:10 615939.9 1.93 3730.9 0.0 55.6816 + 0:39:39 623462.6 0.30 185.2 0.8 58.0183 + 0:39:39 623462.6 0.30 185.2 0.8 58.0183 + 0:41:32 620342.5 0.21 61.2 0.1 56.9876 + 0:41:32 620342.5 0.21 61.2 0.1 56.9876 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:28 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + 0:42:29 622291.2 0.00 0.0 0.2 57.5894 + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 0:42:31 622234.8 0.00 0.0 0.2 57.5880 + 0:43:49 605260.5 0.00 0.0 0.1 51.1072 + 0:43:50 605260.5 0.00 0.0 0.1 51.1072 + 0:43:50 605260.5 0.00 0.0 0.1 51.1072 + 0:45:03 604268.6 0.00 0.0 0.1 50.7387 + 0:45:06 604253.7 0.00 0.0 0.1 50.7337 + 0:45:26 604231.5 0.00 0.0 0.1 50.7282 + 0:45:41 604222.1 0.00 0.0 0.1 50.7261 + 0:45:43 604219.6 0.00 0.0 0.1 50.7252 + 0:46:38 604110.1 0.00 0.0 0.1 50.6835 + 0:46:53 603998.7 0.00 0.0 0.1 50.6460 + 0:47:04 603905.5 0.00 0.0 0.1 50.6102 + 0:47:12 603863.2 0.00 0.0 0.0 50.5947 + 0:47:12 603863.2 0.00 0.0 0.0 50.5947 + 0:47:14 603863.2 0.00 0.0 0.0 50.5947 + 0:47:14 603863.2 0.00 0.0 0.0 50.5947 + 0:52:08 602018.9 0.00 0.0 0.0 49.9772 + 0:54:10 600113.6 0.00 0.0 0.0 49.3812 + 0:54:42 599669.2 0.00 0.0 0.0 49.2665 +Loading db file '/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db' + + +Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios + + + Optimization Complete + --------------------- +Warning: Design 'Vortex' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) + Net 'VX_dmem_controller/dcache/genblk3[1].bank_structure/data_structures/clk': 2967 load(s), 1 driver(s) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Information: State dependent leakage is now switched from off to on. +Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) +Warning: Design has unannotated black box outputs. (PWR-428) +1 +ungroup -all -flatten +Information: Updating graph... (UID-83) +Warning: Design 'Vortex' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) +Warning: Design 'Vortex' inherited license information from design 'VX_warp_scheduler'. (DDB-74) +Information: Added key list 'DesignWare' to design 'Vortex'. (DDB-72) +1 +uniquify +1 +define_name_rules verilog -remove_internal_net_bus -remove_port_bus +1 +change_names -rule verilog -hierarchy +1 +report_qor +Information: Updating design information... (UID-85) +Warning: Design 'Vortex' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) + +**************************************** +Report : qor +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:32 2019 +**************************************** + + + Timing Path Group 'clk' + ----------------------------------- + Levels of Logic: 271.00 + Critical Path Length: 9.97 + Critical Path Slack: 0.00 + Critical Path Clk Period: 10.00 + Total Negative Slack: 0.00 + No. of Violating Paths: 0.00 + Worst Hold Violation: -0.07 + Total Hold Violation: -129.42 + No. of Hold Violations: 2048.00 + ----------------------------------- + + + Cell Count + ----------------------------------- + Hierarchical Cell Count: 0 + Hierarchical Port Count: 0 + Leaf Cell Count: 132902 + Buf/Inv Cell Count: 22545 + Buf Cell Count: 382 + Inv Cell Count: 22163 + CT Buf/Inv Cell Count: 0 + Combinational Cell Count: 129846 + Sequential Cell Count: 3056 + Macro Count: 0 + ----------------------------------- + + + Area + ----------------------------------- + Combinational Area: 124356.059617 + Noncombinational Area: 9450.593859 + Buf/Inv Area: 12040.812023 + Total Buffer Area: 495.07 + Total Inverter Area: 11545.74 + Macro/Black Box Area: 465862.566406 + Net Area: 0.000000 + ----------------------------------- + Cell Area: 599669.219882 + Design Area: 599669.219882 + + + Design Rules + ----------------------------------- + Total Number of Nets: 141970 + Nets With Violations: 3 + Max Trans Violations: 3 + Max Cap Violations: 0 + ----------------------------------- + + + Hostname: gtcad-srv1 + + Compile CPU Statistics + ----------------------------------------- + Resource Sharing: 23.56 + Logic Optimization: 822.54 + Mapping Optimization: 1328.17 + ----------------------------------------- + Overall Compile Time: 3249.38 + Overall Compile Wall Clock Time: 3303.77 + + -------------------------------------------------------------------- + + Design WNS: 0.00 TNS: 0.00 Number of Violating Paths: 0 + + + Design (Hold) WNS: 0.07 TNS: 129.42 Number of Violating Paths: 2048 + + -------------------------------------------------------------------- + + +1 +report_area + +**************************************** +Report : area +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:34 2019 +**************************************** + +Library(s) Used: + + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db) + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (File: /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db) + +Number of ports: 2215 +Number of nets: 141970 +Number of cells: 132948 +Number of combinational cells: 129846 +Number of sequential cells: 3016 +Number of macros/black boxes: 40 +Number of buf/inv: 22545 +Number of references: 437 + +Combinational area: 124356.059617 +Buf/Inv area: 12040.812023 +Noncombinational area: 9450.593859 +Macro/Black Box area: 465862.566406 +Net Interconnect area: 0.000000 + +Total cell area: 599669.219882 +Total area: 599669.219882 +1 +report_hierarchy + +**************************************** +Report : hierarchy +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:35 2019 +**************************************** + +Attributes: + r - licensed design + +Vortex r + ADDF_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + ADDH_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X8B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X7P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X11M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X3P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X7P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X13M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGENI_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGENI_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGEN_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFQL_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQL_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQNL_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQN_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFSQN_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFSQN_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X2P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X3P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X7P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X11M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X16M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + LATQ_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X0P7B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X8B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X0P5A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X6A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4XXXB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X0P5A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X6A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X8A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA211_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA211_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X0P7B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + TIEHI_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + TIELO_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR3_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c +1 +report_cell + +**************************************** +Report : cell +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:35 2019 +**************************************** + +Attributes: + b - black box (unknown) + d - dont_touch + h - hierarchical + mo - map_only + n - noncombinational + r - removable + u - contains unmapped logic + +Cell Reference Library Area Attributes +-------------------------------------------------------------------------------- +U1 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +U2 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U3 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +U4 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U5 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +U6 AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +U7 OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +U8 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U9 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U11 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U12 OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +U13 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U14 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U15 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U16 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U17 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U14 NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_U15 NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_U16 INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U17 BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_U18 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U19 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U20 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U21 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U22 BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U23 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U24 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U25 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U26 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U27 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U28 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U29 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U30 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U31 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U32 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U33 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U34 OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U35 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U36 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U37 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U38 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U39 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U40 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U41 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U42 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U43 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U44 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U45 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U46 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U47 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U48 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U49 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U50 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U51 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U52 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U53 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U54 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U55 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U56 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U57 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U58 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U59 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U60 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U61 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U62 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U63 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U64 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U65 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U66 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U67 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U68 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U69 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U70 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U80 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U81 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U82 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U83 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U84 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U85 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U86 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U87 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U97 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U98 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U99 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U100 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U101 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U102 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U103 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U104 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U105 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U106 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U107 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U108 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U109 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U110 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U111 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U112 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U113 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U114 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U115 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U116 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U117 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U118 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U119 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U120 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U121 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U122 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U123 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U124 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U125 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U126 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U127 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U128 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U129 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U130 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U131 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U132 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U133 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U134 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U135 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U136 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U137 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U138 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U139 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U140 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U141 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U142 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U143 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U144 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U145 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U146 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U147 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U148 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U149 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U150 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U151 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U152 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U153 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U154 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U155 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U156 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U157 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U158 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U159 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U160 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U161 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U162 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U163 NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_U164 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_U165 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U4 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U24 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U26 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U27 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U28 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U29 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U30 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U31 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U32 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U33 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U34 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U35 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U36 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U37 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U38 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U39 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U40 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U41 + NOR4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_dcache_U42 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U44 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U45 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U46 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U47 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U49 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U50 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U51 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U52 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U53 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U54 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U55 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U56 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U57 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U58 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U59 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U60 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U61 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U62 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U63 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U64 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U65 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U66 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U67 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U68 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U69 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U70 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U71 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U72 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U73 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U74 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U75 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U76 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U77 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U78 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U79 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U80 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U81 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U82 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U83 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U84 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U85 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U86 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U87 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U88 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U89 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U91 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U92 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U93 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U94 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U95 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U96 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U97 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U98 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U99 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U125 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U126 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U128 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U130 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U131 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U133 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U135 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U137 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U139 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U140 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U141 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U142 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U143 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U146 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U148 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U149 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U150 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U153 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U177 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U186 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U187 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U188 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U189 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U190 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U195 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U196 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U201 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U202 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U206 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U207 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U212 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U213 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U214 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U215 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U216 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U217 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U218 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U219 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U221 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U222 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U223 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U224 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U225 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U226 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U227 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U228 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U229 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U230 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U231 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U232 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U233 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U234 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U236 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U237 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U238 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U239 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U245 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U247 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U248 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U249 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U250 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U251 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U252 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U253 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U255 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U257 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U262 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U263 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U264 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U265 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U267 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U271 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U273 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U274 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U275 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U276 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U277 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U278 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U279 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U281 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U282 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U284 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U286 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U288 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U291 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U292 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U293 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U296 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U299 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U300 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U301 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U303 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U304 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U305 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U307 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U308 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U309 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U322 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U324 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U327 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U329 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U331 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U334 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U337 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U338 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U339 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U340 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U341 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U342 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U344 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U346 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U347 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U350 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U353 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U354 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U356 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U357 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U359 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U360 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U361 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U362 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U363 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U364 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U365 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U366 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U367 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U368 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U370 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U374 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U375 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U382 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U383 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U385 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U387 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U388 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U389 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U390 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U392 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U394 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U395 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U398 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U399 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U400 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U401 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U402 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U403 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U404 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U405 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U406 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U407 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U408 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U409 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U410 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U411 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U412 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U413 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U415 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U416 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U417 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U418 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U419 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U420 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U421 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U422 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U424 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U425 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U427 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U428 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U429 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U430 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U431 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U432 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U433 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U434 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U435 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U436 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U437 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U439 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U440 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U442 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U443 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U444 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U445 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U447 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U448 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U449 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U450 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U451 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U452 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U454 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U455 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U456 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U457 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U459 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U460 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U462 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U463 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U465 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U466 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U467 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U468 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U469 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U471 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U473 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U474 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U475 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U476 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U477 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U478 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U479 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U480 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U481 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U482 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U483 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U484 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U485 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U486 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U487 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U488 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U489 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U490 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U491 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U492 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U493 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U494 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U496 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U497 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U498 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U499 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U500 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U501 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U502 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U503 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U504 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U505 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U506 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U507 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U508 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U509 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U510 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U511 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U514 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U515 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U516 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U517 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U519 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U520 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U521 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U522 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U523 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U524 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U525 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U526 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U527 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U528 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U529 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U530 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U531 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U532 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U533 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U534 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U535 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U536 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U537 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U538 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U539 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U540 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U542 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U543 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U544 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U545 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U546 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U547 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U549 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U550 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U552 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U553 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U554 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U555 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U556 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U557 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U558 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U559 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U560 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U561 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U562 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U563 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U564 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U565 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U566 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U567 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U568 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U569 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U570 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U571 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U572 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U573 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U574 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U575 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U576 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U577 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U578 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U579 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U580 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U581 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U582 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U583 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U585 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U586 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U587 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U588 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U589 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U590 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U591 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U592 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U593 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U594 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U595 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U596 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U598 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U599 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U600 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U601 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U602 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U603 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U604 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U605 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U606 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U607 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U608 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U610 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U611 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U612 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U613 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U614 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U616 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U617 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U618 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U619 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U620 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U621 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U622 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U623 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U624 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U625 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U626 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U627 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U628 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U629 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U630 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U631 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U632 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U634 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U636 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U637 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U638 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U639 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U640 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U641 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U642 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U643 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U644 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U645 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U646 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U647 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U648 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U649 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U650 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U651 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U652 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U653 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U654 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U655 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U656 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U657 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U658 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U659 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U660 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U661 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U662 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U663 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U664 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U665 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U666 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U667 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U671 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U672 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U674 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U675 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U677 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U678 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U680 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U681 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U683 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U684 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U685 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U686 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U687 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U690 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U692 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U693 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U695 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U696 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U697 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U698 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U700 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U702 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U703 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U705 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U707 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U708 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U710 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U712 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U713 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U715 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U716 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U718 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U719 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U721 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U722 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U724 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U725 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U726 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U728 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U729 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U730 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U731 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U733 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U734 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U736 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U737 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U738 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U739 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U740 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U742 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U743 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U744 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U745 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U746 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U747 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U748 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U749 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U750 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U751 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U752 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U754 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U755 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U758 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U759 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U760 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U761 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U762 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U763 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U764 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U765 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U766 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U767 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U768 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U769 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U770 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U771 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U772 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U773 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U774 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U777 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U779 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U780 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U782 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U783 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U785 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U786 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U788 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U789 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U791 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U793 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U794 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U796 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U797 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U798 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U800 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U801 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U802 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U804 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U805 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U806 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U807 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U808 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U809 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U810 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U811 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U812 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U813 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U814 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U815 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U816 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U817 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U818 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U819 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U820 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U821 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U823 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U824 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U825 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U827 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U828 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U829 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U830 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U831 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U832 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U833 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U834 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U835 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U836 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U838 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U839 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U840 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U841 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U842 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U843 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U845 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U846 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U847 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U848 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U849 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U850 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U851 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U852 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U853 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U856 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U857 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U859 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U861 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U862 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U864 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U865 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U866 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U867 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U868 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U870 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U871 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U872 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U873 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U874 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U876 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U877 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U878 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U880 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U881 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U882 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U884 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U885 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U887 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U888 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U889 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U890 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U892 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U893 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U894 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U895 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U896 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U897 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U898 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U899 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U900 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U901 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U902 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U903 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U904 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U905 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U906 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U907 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U908 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U910 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U911 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U912 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U913 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U914 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U916 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U918 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U919 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U921 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U922 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U924 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U925 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U926 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U928 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U929 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U931 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U932 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U934 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U935 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U936 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U937 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U938 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U939 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U940 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U941 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U942 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U943 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U944 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U945 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U946 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U947 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U948 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U949 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U950 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U951 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U952 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U953 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U954 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U955 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U957 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U958 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U959 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U960 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U961 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U962 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U963 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U964 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U966 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U967 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U968 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U969 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U970 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U972 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U973 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U975 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U977 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U978 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U980 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U981 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U982 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U983 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U984 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U986 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U987 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U988 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U990 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U991 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U992 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U993 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U994 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U996 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U997 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U998 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U999 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1001 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1002 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1004 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1005 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1007 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1008 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1009 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1010 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1011 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1012 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1013 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1014 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1015 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1017 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1018 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1019 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1020 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1021 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1023 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1024 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1025 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1026 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1027 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1028 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1029 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1030 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1031 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1032 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1033 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1034 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1035 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1036 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1037 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1038 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1039 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1040 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1041 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1042 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1043 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1045 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1046 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1047 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1048 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1049 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1050 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1051 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1052 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1053 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1054 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1055 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1056 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1057 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1058 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1061 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1062 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1063 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1064 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1065 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1066 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1067 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1068 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1069 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1070 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1071 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1072 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1073 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1074 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1075 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1076 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1077 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1078 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1080 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1081 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1082 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1083 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1084 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1086 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1087 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1088 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1089 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1090 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1092 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1094 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1095 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1097 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1098 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1099 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1112 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1121 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1124 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1127 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1135 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1165 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1194 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1205 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1211 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1214 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1217 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1220 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1221 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1223 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1237 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1258 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1273 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1279 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1280 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U1281 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1282 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1283 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1284 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1285 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1286 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1287 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1288 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1289 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1290 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1291 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1292 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1293 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1294 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1295 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1296 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1297 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1298 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1299 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1300 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1301 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1303 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1304 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1305 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1306 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1307 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1308 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1309 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1310 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1312 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1313 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1314 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1315 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1316 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1317 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1318 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1319 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1320 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1322 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1323 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1324 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1325 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1326 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1327 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1328 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1330 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1331 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1332 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1333 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1334 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1336 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1337 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1338 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1339 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1341 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1342 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1343 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1344 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1345 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1346 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1347 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1348 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1351 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1352 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1353 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1354 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1355 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1357 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1358 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1359 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1360 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1361 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1362 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1363 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1364 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1365 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1366 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1367 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1368 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1370 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1371 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1372 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1373 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1374 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1376 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1377 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1378 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1379 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1380 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1382 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1383 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1387 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1388 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1389 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1390 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1392 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1393 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1394 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1395 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1396 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1398 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1399 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1400 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1401 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1402 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1403 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1404 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1405 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1406 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1407 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1409 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1411 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1412 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1413 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1414 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1417 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1418 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1419 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1420 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1421 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1423 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1427 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1428 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1429 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1430 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1431 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1432 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1433 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1434 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1435 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1437 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1440 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1441 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1442 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1443 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1444 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1445 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1447 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1448 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1449 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1450 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1453 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1454 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1455 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1457 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1458 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1459 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1460 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1463 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1466 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1467 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1468 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1469 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1470 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1471 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1472 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1474 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1475 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1476 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1477 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1478 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U1479 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1480 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1481 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1482 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1483 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1484 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1485 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1486 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1487 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1488 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1489 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1490 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1491 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1492 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1493 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1494 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1495 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1497 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1498 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1499 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1501 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1502 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1503 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1505 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1506 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1507 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1509 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1511 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1513 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1514 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1515 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1517 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1518 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1519 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1521 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1522 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1523 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1525 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1526 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1528 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1529 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1530 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1531 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1532 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1533 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1534 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1535 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1536 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1538 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1539 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1540 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1542 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1543 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1544 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1546 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1547 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1548 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1550 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1551 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1552 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1553 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1554 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1555 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1556 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1557 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1558 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1559 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1560 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1561 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1562 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1563 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1564 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1565 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1566 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1567 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1568 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1569 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1570 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1572 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1573 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1574 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1575 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1576 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1577 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1578 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1579 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1580 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1581 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1582 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1583 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1584 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1585 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1586 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1587 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1588 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1589 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1590 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1591 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1592 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1593 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1594 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1595 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1596 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1598 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1599 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1600 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1601 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1602 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1603 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1604 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1605 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1606 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1607 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1608 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1609 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1610 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1611 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1612 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1613 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1614 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1615 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1616 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1617 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1618 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1619 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1620 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1621 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1622 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1623 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1624 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1625 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1626 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1627 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1628 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1629 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1630 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1631 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1632 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1633 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1634 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1635 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1636 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1637 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1638 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1639 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1640 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1641 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1642 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1643 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1644 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1645 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1646 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1647 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1648 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1649 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1650 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1651 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1652 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1653 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1654 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1655 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1656 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1657 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1658 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1659 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1660 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1661 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1662 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1663 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1664 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1665 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1666 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1667 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1669 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1671 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1672 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1673 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1674 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1676 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1677 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1678 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1680 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1683 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1684 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1685 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1686 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1687 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1690 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1692 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1693 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1695 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1696 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1697 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1698 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1700 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1703 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1705 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1707 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1708 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1710 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1712 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1713 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1715 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1716 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1718 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1719 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1721 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1722 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1724 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1725 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1726 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1728 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1729 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1730 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1731 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1733 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1734 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1736 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1737 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1738 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1739 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1740 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1742 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1743 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1744 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1745 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1747 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1748 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1750 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1751 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1752 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1754 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1755 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1757 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1759 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1760 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1761 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1762 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1763 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1764 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1765 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1766 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1767 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1768 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1769 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1770 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1771 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1772 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1773 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1774 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1777 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1779 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1780 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1781 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1782 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1783 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1784 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1785 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1786 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1787 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1788 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1789 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1790 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1791 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1793 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1794 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1796 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1797 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1798 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1800 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1801 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1802 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1804 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1805 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1806 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1807 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1808 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1809 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1810 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1811 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1812 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1813 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1814 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1815 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1816 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1817 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1818 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1819 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1820 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1823 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1824 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1825 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1827 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1828 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1829 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1830 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1831 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1832 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1833 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1834 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1835 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1836 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1838 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1839 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1840 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1841 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1842 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1843 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1845 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1846 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1847 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1848 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1849 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1850 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1851 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1852 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1853 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1855 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1856 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1857 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1858 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1859 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1861 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1862 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1864 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1865 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1866 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1867 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1868 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1871 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1872 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1873 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1874 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1876 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1877 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1878 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1880 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1881 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1882 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1884 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1885 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1887 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1888 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1889 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1890 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1892 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1893 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1894 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1895 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1896 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1897 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1899 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1900 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1903 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1904 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1905 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1906 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1907 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1908 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1910 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1911 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1912 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1914 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1916 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1918 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1919 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1921 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1922 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1924 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1925 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1926 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1928 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1929 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1931 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1932 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1934 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1935 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1936 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1937 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1938 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1939 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1940 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1941 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1942 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1943 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1944 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1945 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1946 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1947 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1948 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1949 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1950 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1951 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1952 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1953 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1954 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1955 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1957 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1958 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1959 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1960 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1961 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1962 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1963 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1964 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1966 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1967 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1968 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1969 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1970 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1972 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1973 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1975 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1976 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1977 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1978 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1979 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1980 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1981 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1982 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1983 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1984 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1986 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1987 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1988 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1990 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1991 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1992 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1993 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1994 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1997 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1998 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1999 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2000 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2001 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2004 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2005 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2007 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2008 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2009 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2010 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2011 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2012 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2013 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2014 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2015 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2017 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2018 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2019 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2020 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2021 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2023 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2024 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2025 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2026 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2027 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2028 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2029 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2030 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2031 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2032 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2033 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2034 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2035 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2036 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2037 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2038 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2039 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2040 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2041 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2042 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2043 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2045 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2046 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2047 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2048 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2049 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2050 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2051 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2052 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2053 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2054 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2055 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2056 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2057 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2058 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2059 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2069 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2070 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2071 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2072 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2073 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2074 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2075 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2076 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2077 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2078 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2080 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2081 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2082 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2083 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2084 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2086 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2087 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2088 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2089 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2090 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2094 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2095 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2097 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2098 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2099 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2101 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2107 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2114 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2120 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2123 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2127 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2130 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2133 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2140 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2147 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2154 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2160 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2167 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2173 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2180 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2187 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2193 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2198 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2201 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2204 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2211 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2214 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2218 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2220 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2221 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2225 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2232 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2238 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2245 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2251 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2257 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2258 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2265 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2272 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2273 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2278 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2279 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2282 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2283 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2284 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2290 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2296 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2297 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2303 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2307 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2308 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2309 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2310 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2312 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2314 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2315 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2316 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2317 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2318 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2319 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2322 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2323 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2324 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2325 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2327 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2328 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2330 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2331 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2332 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2334 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2336 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2337 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2339 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2341 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2342 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2343 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2344 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2345 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2346 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2347 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2348 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2350 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2351 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2352 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2353 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2354 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2355 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2356 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2357 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2360 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2361 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2362 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2363 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2364 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2365 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2368 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2370 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2371 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2372 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2373 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2374 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2376 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2377 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2379 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2382 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2383 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2384 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2387 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2388 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2389 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2390 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2393 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2394 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2395 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2396 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2398 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2400 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2401 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2402 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2403 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2404 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2405 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2407 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2409 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2411 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2412 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2416 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2417 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2421 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2423 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2426 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2427 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2430 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2431 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2433 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2434 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2435 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2436 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2437 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2439 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2440 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2443 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2444 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2445 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2446 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2449 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2450 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2453 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2455 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2457 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2459 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2460 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2463 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2466 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2467 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2468 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2469 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2471 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2472 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2473 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2474 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2475 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2476 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2477 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2478 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2479 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2480 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2481 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2482 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2483 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2484 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2485 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2486 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2487 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2488 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2489 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2490 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2491 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2492 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2493 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2494 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2495 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2496 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2497 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2498 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2499 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2500 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2501 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2502 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2503 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2504 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2505 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2506 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2507 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2508 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2509 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2511 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2512 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2513 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2514 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2516 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2517 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2518 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2520 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2521 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2522 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2523 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2524 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2525 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2526 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2527 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2528 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2529 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2530 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2531 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2532 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2533 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2534 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2535 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2536 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2537 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2538 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2539 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2540 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2541 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2542 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2543 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2544 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2545 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2546 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2547 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2548 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2549 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2550 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2551 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2552 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2553 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2554 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2555 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2556 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2557 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2559 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2560 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2561 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2562 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2563 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2564 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2565 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2566 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2567 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2568 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2569 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2570 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2571 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2572 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2573 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2574 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2575 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2576 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2577 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2578 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2579 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2580 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2581 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2582 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2583 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2584 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2585 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2586 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2587 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2588 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2589 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2590 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2591 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2592 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2593 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2595 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2596 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2598 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2599 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2600 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2601 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2602 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2603 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2604 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2605 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2607 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2608 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2610 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2611 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2612 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2613 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2614 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2615 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2616 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2617 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2618 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2619 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2620 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2621 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2622 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2623 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2624 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2625 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2626 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2627 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2628 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2629 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2630 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2631 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2632 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2634 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2635 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2636 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2637 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2638 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2639 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2640 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2641 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2642 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2643 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2644 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2645 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2646 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2647 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2648 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2649 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2650 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2651 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2652 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2653 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2654 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2655 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2656 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2657 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2658 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2659 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2660 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2661 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2662 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2663 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2664 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2665 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2666 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2667 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2668 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2669 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2670 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2671 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2672 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2673 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2674 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2676 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2677 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2678 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2679 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2680 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2682 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2683 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2684 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2685 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2686 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2687 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2688 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2689 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2690 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2692 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2693 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2695 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2696 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2697 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2698 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2699 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2700 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2702 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2703 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2705 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2706 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2707 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2708 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2709 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2710 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2712 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2713 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2715 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2716 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2718 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2719 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2721 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2722 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2724 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2725 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2726 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2727 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2728 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2729 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2730 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2731 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2733 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2734 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2736 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2737 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2738 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2739 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2740 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2742 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2743 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2744 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2745 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2747 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2748 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2750 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2751 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2752 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2753 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2754 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2755 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2756 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2757 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2759 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2760 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2761 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2762 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2763 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2764 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2765 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2766 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2767 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2768 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2769 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2770 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2771 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2772 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2773 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2774 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2775 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2777 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2779 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2780 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2782 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2783 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2785 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2786 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2788 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2789 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2791 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2792 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2793 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2794 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2796 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2797 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2798 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2799 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2800 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2801 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2802 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2803 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2804 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2805 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2806 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2807 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2808 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2809 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2810 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2811 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2812 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2813 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2814 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2815 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2816 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2817 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2818 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2819 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2820 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2822 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2823 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2824 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2825 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2826 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2827 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2828 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2829 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2830 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2831 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2832 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2833 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2834 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2835 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2836 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2837 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2838 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2839 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2840 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2841 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2842 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2843 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2845 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2846 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2847 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2848 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2849 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2850 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2851 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2852 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2853 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2854 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2856 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2857 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2859 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2860 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2861 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2862 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2863 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2864 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2865 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2866 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2867 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2868 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2869 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2871 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2872 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2873 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2874 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2875 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2876 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2877 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2878 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2880 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2881 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2882 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2883 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2884 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2885 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2886 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2887 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2888 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2889 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2890 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2892 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2893 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2894 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2895 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2896 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2897 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2899 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2900 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2902 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2903 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2904 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2905 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2906 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2907 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2908 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2910 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2911 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2912 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2913 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2914 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2916 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2917 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2918 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2919 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2920 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2921 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2922 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2923 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2924 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2925 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2926 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2928 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2929 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2931 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2932 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2934 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2935 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2936 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2937 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2938 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2939 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2940 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2941 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2942 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2943 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2944 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2945 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2946 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2947 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2948 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2949 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2950 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2951 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2952 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2953 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2954 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2955 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2957 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2958 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2959 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2960 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2961 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2962 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2963 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2964 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2965 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2966 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2967 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2968 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2969 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2970 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2971 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2972 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2973 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2974 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2975 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2977 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2978 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2980 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2981 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2982 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2983 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2984 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2985 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2986 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2987 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2988 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2989 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2990 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2991 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2992 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2993 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2994 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2996 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2997 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2998 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2999 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3001 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3002 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3004 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3005 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3007 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3008 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3009 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3010 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3011 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3012 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3013 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_evict_addr_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_genblk1_0__choose_thread_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U4 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U5 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U8 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U11 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U4 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U5 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U8 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U11 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U4 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U5 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U8 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U11 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U3 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U5 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U8 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U11 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U3 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U5 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U6 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U11 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U3 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U5 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U4 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U6 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U11 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U7 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U9 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U10 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U11 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U12 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U14 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U15 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U16 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U17 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U20 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U21 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U22 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U23 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U24 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U25 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U26 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U27 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U28 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U29 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U30 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U31 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U32 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U33 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U34 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U35 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U36 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U37 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U38 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U39 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U40 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U41 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U42 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U43 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U44 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U45 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U46 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U47 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U48 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U50 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U51 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U52 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U60 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U61 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U62 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U63 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U64 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U73 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U74 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U75 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U76 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U77 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U78 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U86 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U87 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U88 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U89 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U90 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U91 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U99 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U112 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U113 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U114 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U126 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U127 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U128 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U129 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U138 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U142 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U143 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U144 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U151 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U155 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U156 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U165 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U169 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U170 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U171 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U183 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U184 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U185 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U194 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U198 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U199 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U200 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U204 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U208 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U211 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U212 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U213 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U214 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U215 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U216 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U219 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U221 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U223 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U224 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U227 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U228 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U230 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U231 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U233 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U234 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U237 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U240 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U243 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U245 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U246 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U247 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U254 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U255 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U256 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U300 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U304 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U305 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U307 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U309 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U311 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U314 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U319 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U324 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U326 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U329 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U337 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U341 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U350 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U352 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U354 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U415 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U416 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U417 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U421 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U424 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U10 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U11 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_1__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U9 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U10 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U11 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U13 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U14 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U15 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U16 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U17 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U18 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U19 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U20 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U21 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U22 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U24 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U25 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U26 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U27 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U28 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U29 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U30 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U31 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U32 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U33 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U34 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U35 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U36 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U37 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U38 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U39 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U40 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U41 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U42 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U43 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U44 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U45 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U46 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U54 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U55 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U56 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U57 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U58 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U59 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U60 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U61 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U62 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U64 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U65 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U66 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U67 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U68 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U69 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U70 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U71 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U72 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U80 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U81 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U82 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U83 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U84 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U85 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U93 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U94 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U95 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U96 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U97 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U98 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U119 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U124 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U132 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U133 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U141 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U144 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U145 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U146 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U158 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U159 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U172 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U173 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U174 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U186 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U187 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U188 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U197 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U201 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U202 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U203 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U209 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U210 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U213 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U214 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U215 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U217 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U222 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U224 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U225 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U228 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U233 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U234 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U237 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U240 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U245 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U256 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U300 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U302 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U313 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U315 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U319 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U326 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U329 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U341 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U352 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U415 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U23 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_2__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U6 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U7 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U9 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U10 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U11 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U13 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U14 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U19 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U20 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U22 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U23 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U24 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U25 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U26 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U27 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U35 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U36 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U37 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U38 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U39 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U40 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U49 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U50 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U51 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U52 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U53 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U61 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U62 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U63 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U64 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U66 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U74 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U75 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U76 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U77 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U78 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U79 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U87 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U88 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U89 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U90 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U91 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U92 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U113 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U140 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U141 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U142 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U154 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U155 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U168 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U169 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U170 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U183 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U184 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U185 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U194 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U198 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U199 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U200 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U205 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U209 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U212 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U213 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U214 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U215 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U217 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U222 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U224 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U225 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U228 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U232 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U237 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U242 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U245 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U256 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U300 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U302 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U313 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U315 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U319 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U326 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U329 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U341 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U352 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U415 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U10 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U11 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_3__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U10 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U11 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U12 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U13 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U14 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U15 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U17 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U18 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U19 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U22 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U23 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U24 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U25 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U26 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U27 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U28 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U29 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U30 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U31 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U32 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U33 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U34 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U35 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U36 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U37 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U38 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U39 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U40 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U41 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U50 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U51 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U52 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U53 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U54 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U62 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U63 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U64 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U66 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U67 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U75 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U76 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U77 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U78 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U79 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U80 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U88 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U89 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U90 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U91 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U92 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U93 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U114 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U115 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U116 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U117 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U127 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U128 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U129 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U130 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U143 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U144 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U145 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U154 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U158 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U173 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U174 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U175 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U182 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U186 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U187 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U188 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U197 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U201 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U202 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U203 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U211 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U215 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U217 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U218 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U220 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U222 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U224 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U225 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U228 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U232 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U235 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U237 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U240 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U243 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U245 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U254 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U255 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U256 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U257 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U259 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U261 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U263 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U265 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U267 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U269 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U271 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U273 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U275 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U277 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U279 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U281 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U283 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U284 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U285 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U287 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U289 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U291 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U293 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U295 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U297 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U300 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U302 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U305 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U307 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U309 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U310 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U311 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U313 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U314 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U319 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U321 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U324 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U326 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U328 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U337 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U338 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U341 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U350 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U352 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U415 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U416 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U417 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U418 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U419 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U421 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U424 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U426 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U427 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U428 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_4__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U8 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U11 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U12 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U13 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U14 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U15 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U17 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U18 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U19 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U22 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U23 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U24 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U25 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U26 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U27 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U28 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U29 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U30 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U31 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U32 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U33 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U34 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U35 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U36 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U37 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U38 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U39 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U40 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U41 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U42 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U43 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U44 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U45 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U46 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U47 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U49 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U50 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U51 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U52 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U53 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U54 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U55 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U56 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U57 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U58 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U60 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U61 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U62 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U63 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U64 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U65 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U66 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U67 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U68 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U76 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U77 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U78 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U79 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U80 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U81 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U89 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U90 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U91 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U92 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U93 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U94 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U102 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U115 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U116 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U128 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U129 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U130 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U141 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U142 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U143 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U156 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U157 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U158 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U165 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U168 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U169 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U170 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U182 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U183 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U184 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U197 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U198 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U210 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U211 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U212 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U213 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U214 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U215 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U219 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U220 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U222 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U223 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U225 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U226 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U227 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U229 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U230 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U232 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U233 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U236 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U239 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U242 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U245 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U256 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U305 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U307 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U309 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U314 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U321 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U324 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U328 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U337 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U350 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U415 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U10 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U11 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_5__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U8 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U9 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U11 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U12 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U13 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U14 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U15 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U17 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U25 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U26 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U27 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U28 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U29 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U30 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U38 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U39 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U41 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U42 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U43 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U44 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U45 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U46 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U47 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U48 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U49 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U50 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U51 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U52 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U54 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U55 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U56 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U57 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U58 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U59 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U60 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U61 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U62 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U63 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U64 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U65 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U66 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U67 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U68 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U69 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U70 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U71 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U72 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U73 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U74 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U75 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U76 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U77 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U78 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U79 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U80 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U81 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U82 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U83 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U84 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U85 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U86 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U87 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U88 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U89 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U90 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U91 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U92 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U93 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U94 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U95 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U96 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U97 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U98 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U99 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U102 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U106 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U107 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U108 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U109 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U118 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U121 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U122 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U123 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U124 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U133 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U137 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U138 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U139 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U148 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U152 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U153 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U154 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U163 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U167 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U168 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U169 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U178 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U182 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U183 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U184 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U196 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U197 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U198 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U209 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U210 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U211 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U212 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U213 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U214 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U215 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U217 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U219 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U221 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U222 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U224 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U225 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U226 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U232 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U235 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U237 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U238 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U241 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U244 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U246 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U256 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U300 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U302 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U313 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U315 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U319 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U326 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U329 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U341 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U352 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U415 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U10 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U11 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_6__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U5 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U9 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U10 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U11 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U12 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U13 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U14 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U19 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U20 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U22 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U23 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U24 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U25 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U26 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U27 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U28 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U29 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U30 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U31 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U32 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U33 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U34 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U35 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U36 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U37 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U38 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U39 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U40 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U41 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U42 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U44 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U45 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U46 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U47 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U49 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U50 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U51 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U52 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U53 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U54 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U55 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U57 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U58 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U59 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U60 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U61 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U62 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U63 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U64 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U66 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U67 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U68 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U69 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U70 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U71 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U72 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U73 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U74 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U75 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U76 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U77 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U78 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U79 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U80 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U81 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U82 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U83 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U84 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U85 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U86 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U87 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U88 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U89 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U90 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U91 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U92 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U93 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U94 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U95 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U96 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U97 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U98 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U99 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U107 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U112 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U113 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U114 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U119 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U123 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U126 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U127 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U128 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U129 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U138 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U142 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U143 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U144 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U156 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U157 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U158 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U167 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U171 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U172 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U181 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U185 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U186 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U194 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U198 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U199 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U200 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U205 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U209 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U212 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U213 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U214 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U215 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U217 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U222 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U224 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U225 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U228 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U232 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U239 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U242 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U244 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U246 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U256 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U305 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U307 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U309 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U314 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U321 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U324 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U328 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U337 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U350 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U415 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_7__bank_structure_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U5 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U9 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U12 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U15 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U16 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U19 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U21 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U22 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U23 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U24 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U25 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U26 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U27 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U28 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U29 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U30 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U31 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U32 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U33 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U34 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U35 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U36 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U37 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U38 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U39 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U40 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U41 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U42 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U43 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U44 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U45 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U46 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U47 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U48 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U49 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U51 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U52 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U53 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U54 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U55 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U56 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U57 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U59 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U60 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U61 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U62 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U63 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U64 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U65 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U66 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U67 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U68 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U69 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U77 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U78 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U79 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U80 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U81 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U82 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U90 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U91 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U92 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U93 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U94 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U95 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U107 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U108 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U111 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U112 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U113 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U114 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U119 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U123 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U126 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U127 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U128 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U133 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U137 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U141 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U142 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U143 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U155 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U156 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U165 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U169 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U170 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U171 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U183 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U184 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U185 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U194 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U197 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U198 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U199 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U210 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U211 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U212 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U213 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U214 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U215 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U219 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U221 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U222 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U224 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U225 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U226 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U232 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U235 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U237 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U238 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U241 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U244 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U246 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U250 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U252 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U253 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U256 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U258 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U260 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U262 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U264 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U266 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U268 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U270 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U272 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U280 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U282 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U284 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U286 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U288 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U290 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U292 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U294 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U296 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U298 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U299 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U300 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U301 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U302 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U303 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U304 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U306 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U308 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U310 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U312 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U313 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U315 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U316 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U317 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U318 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U319 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U320 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U322 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U323 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U326 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U327 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U329 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U330 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U331 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U332 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U333 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U334 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U335 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U336 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U338 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U339 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U340 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U341 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U342 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U343 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U344 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U345 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U346 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U347 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U348 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U349 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U351 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U352 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U353 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U354 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U355 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U356 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U357 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U358 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U359 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U360 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U361 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U362 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U363 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U364 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U365 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U366 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U367 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U368 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U369 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U370 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U371 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U372 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U373 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U374 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U375 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U376 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U377 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U378 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U379 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U380 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U381 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U382 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U383 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U384 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U385 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U386 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U387 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U388 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U389 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U390 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U391 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U392 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U393 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U394 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U395 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U396 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U397 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U398 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U399 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U400 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U401 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U402 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U403 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U404 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U405 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U406 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U407 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U408 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U409 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U410 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U411 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U412 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U413 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U414 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U415 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U431 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U10 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U11 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U31 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U32 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U33 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U40 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U41 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U43 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U44 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U45 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U46 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_get_miss_index_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U5 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_get_miss_index_U6 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_get_miss_index_U7 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_get_miss_index_U8 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_get_miss_index_U9 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_get_miss_index_U10 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_get_miss_index_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_get_miss_index_U12 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_get_miss_index_U13 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_get_miss_index_U14 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_miss_addr_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_multip_banks_U2 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U3 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U6 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U8 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U11 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U14 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U16 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U18 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U20 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U21 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U23 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U26 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U27 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U28 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U29 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U30 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U31 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U32 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U33 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U34 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U35 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U36 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U37 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U38 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U39 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U40 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U41 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U42 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U43 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U44 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U45 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U46 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U47 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U48 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U49 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_state_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_state_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_state_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_state_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_U3 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U4 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U8 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U15 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U16 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U17 + NOR4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_shared_memory_U18 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U19 + NOR4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_shared_memory_U20 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U21 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U22 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U23 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U24 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U25 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U26 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U27 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U28 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U29 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U30 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U31 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U32 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U33 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U34 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U35 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U36 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U37 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U38 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U39 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U40 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U41 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U46 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U47 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U48 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U49 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U50 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U51 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U52 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U53 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U54 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U55 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U56 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U57 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U58 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U59 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U60 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U61 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U62 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U63 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U77 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U78 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U79 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U80 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U81 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U82 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U83 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U84 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U85 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U86 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U87 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U88 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U89 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U90 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U91 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U92 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U93 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U94 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U95 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U96 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U97 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U98 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U99 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U102 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U103 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U112 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U113 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U114 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U115 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U116 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U117 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U118 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U119 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U120 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U121 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U122 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U123 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U125 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U126 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U127 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U128 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U129 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U130 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U131 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U132 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U139 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U150 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U151 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U152 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U153 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U154 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U155 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U156 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U157 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U158 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U159 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U160 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U161 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U164 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U165 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U167 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U168 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U170 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U171 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U172 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U173 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U174 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U177 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U179 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U180 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U181 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U182 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U183 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U184 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U185 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U186 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U188 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U189 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U190 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U191 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U192 + NOR3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U195 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U197 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U198 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U199 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U200 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U201 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U202 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U203 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U204 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U205 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U206 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U208 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U209 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U210 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U211 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U213 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U214 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U215 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U216 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U217 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U219 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U220 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U221 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U222 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U224 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U227 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U228 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U229 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U231 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U238 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U247 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U250 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U251 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U252 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U254 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U255 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U256 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U257 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U259 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U261 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U263 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U265 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U266 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U267 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U268 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U270 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U271 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U272 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U273 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U274 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U275 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U276 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U277 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U278 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U279 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U280 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U281 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U282 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U283 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U284 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U285 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U286 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U287 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U288 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U289 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U290 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U292 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U295 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U296 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U297 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U298 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U300 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U302 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U304 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U305 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U306 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U308 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U310 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U311 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U313 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U315 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U317 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U319 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U321 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U323 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U325 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U327 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U329 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U331 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U333 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U335 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U337 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U339 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U340 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U342 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U344 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U346 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U348 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U350 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U352 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U354 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U356 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U357 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U358 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U359 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U360 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U361 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U362 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U363 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U364 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U365 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U366 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U367 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U368 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U369 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U370 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U371 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U372 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U373 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U374 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U375 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U376 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U377 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U378 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U379 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U380 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U381 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U382 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U383 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U384 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U385 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U386 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U387 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U388 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U389 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U390 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U391 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U392 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U417 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U418 + OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U419 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U420 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U421 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U422 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U423 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U424 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U425 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U426 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U427 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U428 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U429 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U430 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U431 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U439 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U440 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U441 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U442 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U443 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U444 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U445 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U454 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U455 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U456 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U457 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U458 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U459 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U460 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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0.810000 +VX_dmem_controller_shared_memory_U641 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U642 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U643 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U644 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U645 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U646 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U647 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U648 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U649 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U650 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U651 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U652 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U653 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U654 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U655 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U656 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U657 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U658 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U659 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U660 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U661 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U662 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U663 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U664 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U665 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U666 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U667 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U668 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U669 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U670 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U671 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U672 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U673 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U674 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U676 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U677 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U678 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U680 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U683 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U684 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U685 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U686 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U687 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U690 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U692 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U693 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U695 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U696 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U697 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U698 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U700 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U703 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U705 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U707 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U708 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U709 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U710 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U712 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U713 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U715 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U716 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U718 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U719 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U721 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U722 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U723 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U724 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U725 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U726 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U728 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U729 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U730 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U731 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U732 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U733 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U734 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U735 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U736 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U737 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U738 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U739 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U740 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U742 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U743 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U744 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U745 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U747 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U748 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U749 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U750 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U751 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U752 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U754 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U755 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U758 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U766 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U767 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U769 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U770 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U771 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U772 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U871 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U872 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U873 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U874 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U876 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U877 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U878 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U880 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U881 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U882 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U884 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U885 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U887 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U888 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U889 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U890 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U892 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U893 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U894 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U895 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U896 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U897 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U899 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U900 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U903 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U904 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U905 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U906 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U907 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U908 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U910 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U911 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U912 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U914 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U915 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U916 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U918 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U919 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U921 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U922 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U924 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U925 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U926 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U928 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U929 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U931 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U932 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U934 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U935 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U936 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U937 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U938 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U939 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U940 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U941 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U942 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U943 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U944 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U945 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U946 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U947 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U948 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U949 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U950 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U951 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U952 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U953 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U954 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U955 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U957 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U958 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U959 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U960 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U961 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U962 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U963 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U964 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U966 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U967 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U968 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U969 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U970 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U972 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U973 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U975 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U976 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U977 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U978 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U980 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U981 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U982 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U983 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U984 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U986 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U987 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U988 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U990 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U991 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U992 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U993 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U994 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U995 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U997 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U998 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U999 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1001 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1004 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1005 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1007 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1008 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1009 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1010 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1011 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1012 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1013 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1014 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1015 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1017 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1018 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1019 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1020 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1021 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1023 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1024 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1025 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1026 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1027 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1028 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1029 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1030 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1031 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1032 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1033 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1034 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1035 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1036 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1037 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1038 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1039 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1040 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1041 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1042 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1043 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1045 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1046 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1047 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1048 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1049 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1050 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1051 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1052 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1053 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1054 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1055 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1056 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1057 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1058 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1061 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1062 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1063 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1064 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1065 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1066 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1067 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1068 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1069 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1070 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1071 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1072 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1073 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1074 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1075 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1076 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1077 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1078 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1080 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1081 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1082 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1083 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1084 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1086 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1087 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1088 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1089 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1090 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1092 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1093 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1094 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1095 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1097 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1098 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1099 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1101 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1113 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1127 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1132 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1138 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1144 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1150 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1152 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1164 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1179 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1185 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1191 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1204 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1210 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1214 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1217 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1219 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1220 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1221 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1224 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1230 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1232 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1245 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1248 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1253 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1254 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1259 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1260 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1261 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1265 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1271 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1275 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1277 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1280 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1283 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1292 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1296 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1297 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1303 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1308 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1309 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1310 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1312 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1314 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1315 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1316 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1317 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1319 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1320 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1321 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1322 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1323 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1324 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1325 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1327 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1328 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1330 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1331 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1333 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1334 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1336 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1337 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1339 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1341 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1342 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1343 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1344 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1346 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1347 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1352 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1353 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1354 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1357 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1359 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1360 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1362 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1363 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1364 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1365 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1368 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1370 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1371 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1373 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1374 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1375 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1376 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1377 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1380 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1383 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1386 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1387 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1388 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1389 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1390 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1393 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1395 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1396 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1400 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1401 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1402 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1403 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1404 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1405 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1406 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1407 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1409 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1410 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1411 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1412 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1413 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1417 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1421 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1423 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1427 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1428 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1430 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1431 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1433 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1434 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1435 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1437 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1438 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1440 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1441 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1443 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1444 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1445 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1448 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1449 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1450 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1451 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1453 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1455 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1457 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1458 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1460 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1461 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1463 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1465 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1466 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1467 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1468 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1469 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1471 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1472 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1473 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1474 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1475 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1476 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1477 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1478 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1479 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1480 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1481 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1482 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1483 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1484 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1485 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1486 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1487 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1488 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1489 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1490 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1491 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1492 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1493 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1494 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1495 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1496 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1497 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1498 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1499 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1500 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1501 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1502 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1503 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1504 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1505 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1506 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1507 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1508 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1509 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1511 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1512 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1513 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1514 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1515 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1516 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1517 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1518 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1519 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1520 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1521 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1522 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1523 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1524 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1525 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1526 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1527 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1528 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1529 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1530 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1531 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1532 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1533 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1534 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1535 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1536 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1537 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1538 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1539 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1540 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1541 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1542 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1543 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1544 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1545 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1546 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1547 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1548 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1549 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1550 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1551 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1552 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1553 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1554 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1555 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1556 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1557 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1558 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1559 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1560 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1561 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1562 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1563 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1564 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1565 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1566 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1567 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1568 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1569 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1570 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1571 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1572 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1573 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1574 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1575 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1576 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1577 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1578 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1579 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1580 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1581 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1583 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1584 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1585 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1586 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1587 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1588 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1590 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1591 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1593 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1594 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1595 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1596 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1598 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1599 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1600 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1601 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1602 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1603 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1604 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1605 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1606 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1607 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1608 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1610 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1611 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1612 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1613 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1614 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1615 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1616 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1617 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1618 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1619 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1620 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1621 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1622 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1623 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1624 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1625 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1626 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1627 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1628 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1629 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1630 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1631 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1632 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1634 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1636 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1637 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1638 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1639 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1640 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1641 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1642 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1643 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1644 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1645 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1646 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1647 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1648 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1649 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1650 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1651 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1652 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1653 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1654 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1655 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1656 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1657 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1658 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1659 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1660 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1661 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1662 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1663 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1664 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1665 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1666 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1667 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1671 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1672 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1674 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1677 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1678 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1680 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1683 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1684 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1685 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1686 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1687 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1689 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1690 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1692 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1693 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1695 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1696 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1697 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1698 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1700 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1703 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1705 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1707 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1708 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1710 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1711 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1712 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1713 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1715 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1716 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1718 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1719 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1721 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1722 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1724 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1725 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1726 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1728 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1729 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1730 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1731 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1733 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1734 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1736 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1737 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1738 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1739 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1740 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1741 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1742 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1743 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1744 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1745 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1747 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1748 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1750 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1751 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1752 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1753 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1754 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1755 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1759 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1760 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1761 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1762 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1763 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1764 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1765 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1766 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1767 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1768 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1769 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1770 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1771 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1772 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1773 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1774 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1776 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1777 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1778 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1779 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1780 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1782 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1783 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1784 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1785 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1786 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1788 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1789 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1791 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1793 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1794 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1795 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1796 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1797 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1798 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1800 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1801 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1802 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1804 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1805 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1806 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1807 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1808 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1809 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1810 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1811 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1812 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1813 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1814 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1815 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1816 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1817 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1818 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1819 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1820 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1823 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1824 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1825 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1827 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1828 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1829 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1830 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1831 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1832 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1833 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1834 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1835 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1836 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1838 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1839 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1840 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1841 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1842 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1843 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1845 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1846 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1847 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1848 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1849 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1850 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1851 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1852 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1853 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1856 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1857 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1859 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1861 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1862 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1864 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1865 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1866 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1867 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1868 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1869 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1871 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1872 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1873 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1874 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1876 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1877 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1878 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1880 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1881 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1882 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1884 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1885 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1887 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1888 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1889 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1890 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1892 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1893 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1894 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1895 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1896 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1897 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1899 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1900 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1903 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1904 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1905 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1906 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1907 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1908 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1910 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1911 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1912 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1914 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1915 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1916 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1918 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1919 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1921 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1922 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1924 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1925 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1926 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1927 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1928 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1929 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1931 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1932 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1933 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1934 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1935 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1936 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1937 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1938 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1939 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1940 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1941 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1942 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1943 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1944 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1945 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1946 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1947 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1948 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1949 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1950 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1951 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1952 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1953 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1954 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1955 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1956 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1957 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1958 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1959 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1960 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1961 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1962 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1963 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1964 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1966 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1967 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1968 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1969 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1970 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1972 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1973 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1975 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1977 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1978 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1980 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1981 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1982 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1983 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1984 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1986 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1987 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1988 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1990 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1991 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1992 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1993 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1994 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1997 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1998 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1999 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2000 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2001 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2003 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2004 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2005 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2006 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2007 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2008 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2009 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2010 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2011 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2012 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2013 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2014 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2015 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2017 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2054 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2055 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2056 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2057 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2058 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2061 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2062 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2063 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2064 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2065 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2066 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2067 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2068 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2069 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2070 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2071 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2072 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2073 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2074 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2075 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2076 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2077 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2078 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2080 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2081 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2082 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2083 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2084 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2086 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2087 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2088 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2089 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2090 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2092 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2094 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2095 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2097 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2098 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2099 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2103 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2109 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2111 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2115 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2121 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2122 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2123 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2127 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2132 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2136 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2138 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2140 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2142 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2143 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2144 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2145 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2147 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2148 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2149 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2150 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2151 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2154 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2155 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2156 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2157 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2158 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2160 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2161 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2162 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2164 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2165 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2167 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2168 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2170 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2171 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2172 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2173 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2174 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2175 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2177 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2181 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2182 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2183 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2184 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2185 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2186 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2187 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2188 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2189 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2190 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2191 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2192 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2195 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2196 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2197 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2198 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2199 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2200 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2202 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2203 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2204 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2205 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2206 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2207 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2208 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2209 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2210 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2211 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2212 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2213 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2214 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2215 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2220 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2221 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2222 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2223 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2224 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2225 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2226 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2227 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2228 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2229 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2231 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2233 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2237 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2238 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2240 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2244 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2247 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2248 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2250 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2251 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2252 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2254 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2255 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2256 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2257 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2258 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2259 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2260 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2261 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2262 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2263 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2264 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2265 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2266 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2267 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2268 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2269 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2270 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2271 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2272 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2273 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2274 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2275 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2276 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2277 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2278 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2279 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2280 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2281 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2282 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2283 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2284 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2285 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2286 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2287 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2288 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2289 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2290 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2291 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2292 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2293 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2294 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2295 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2296 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2297 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2298 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2299 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2300 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2301 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2302 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2303 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2304 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2305 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2306 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2307 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2309 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2311 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2313 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2315 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2317 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2319 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2321 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2323 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2325 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2327 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2329 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2331 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2333 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2335 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2336 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2338 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2340 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2342 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2344 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2346 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2348 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2350 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2352 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2354 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2356 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2357 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2358 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2360 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2362 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2364 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2366 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2367 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2368 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2370 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2372 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2374 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2376 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2377 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2378 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2380 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2381 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2382 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2384 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2385 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2387 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2389 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2391 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2393 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2395 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2397 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2399 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2400 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2401 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2402 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2403 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2405 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2406 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2407 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2408 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2409 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2410 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2411 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2412 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2413 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2414 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2415 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2416 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2417 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2418 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2419 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2420 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2421 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2422 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2423 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2424 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2425 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2426 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2427 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2428 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2429 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2430 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2431 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2432 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2433 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2434 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2435 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2436 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2437 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2438 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2439 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2440 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2441 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2442 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2443 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2444 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2445 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2446 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2447 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2448 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2449 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2450 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2451 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2452 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2453 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2454 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2455 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2456 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2457 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2458 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2459 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2460 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2461 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2462 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2463 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2464 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2465 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2466 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2467 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2468 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2469 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2470 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2471 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2472 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2473 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2474 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2475 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2476 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2477 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2478 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2479 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2480 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2481 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2482 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2483 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2484 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2485 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2486 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2487 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2488 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2489 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2490 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2491 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2492 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2493 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2494 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2495 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2496 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2498 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2499 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2501 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2502 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2504 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2505 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2506 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2508 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2510 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2512 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2514 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2516 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2518 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2520 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2522 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2524 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2526 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2528 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2530 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2531 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2533 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2535 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2537 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2539 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2541 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2543 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2545 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2547 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2549 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2551 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2553 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2555 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2557 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2559 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2560 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2561 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2562 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2563 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2564 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2565 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2566 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2567 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2568 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2569 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2570 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2571 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2572 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2573 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2574 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2575 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2576 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2577 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2578 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2579 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2580 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2581 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2582 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2583 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2584 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2585 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2586 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2587 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2588 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2589 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2590 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2591 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2592 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2593 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2594 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2595 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2596 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2597 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2598 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2599 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2600 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2601 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2602 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2603 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2604 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2605 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2606 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2607 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2608 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2609 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2610 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2611 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2612 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2613 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2614 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2615 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2616 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2617 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2618 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2619 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2620 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2621 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2622 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2623 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2624 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2625 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2626 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2627 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2628 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2629 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2630 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2631 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2632 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2633 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2634 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2635 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2636 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2637 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2638 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2639 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2640 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2641 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2642 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2643 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2644 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2645 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2646 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2647 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2648 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2649 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2650 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2651 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2652 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2653 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2654 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2655 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2656 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2657 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2658 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2659 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2660 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2661 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2662 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2663 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2664 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2665 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2666 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2667 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2668 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2669 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2670 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2671 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2672 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2673 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2674 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2675 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2676 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2677 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2678 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2679 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2680 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2681 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2682 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2683 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2684 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2685 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2686 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2687 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2688 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2689 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2690 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2691 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2692 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2693 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2694 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2695 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2696 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2697 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2698 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2699 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2700 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2701 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2702 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2703 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2704 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2705 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2706 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2707 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2708 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2709 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2710 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2711 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2712 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2713 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2714 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2715 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2716 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2717 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2718 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2719 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2720 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2721 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2722 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2723 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2724 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2725 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2726 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2727 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2728 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2729 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2730 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2731 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2732 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2733 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2734 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2735 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2736 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2737 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2738 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2739 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2740 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2741 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2742 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2743 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2744 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2745 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2746 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2747 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2748 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2749 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2750 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2751 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2752 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2753 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2754 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2755 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2756 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2757 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2758 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2759 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2760 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2761 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2762 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2763 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2764 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2765 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2766 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2767 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2768 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2769 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2770 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2771 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2772 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2773 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2774 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2775 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2776 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2777 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2778 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2779 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2780 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2781 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2782 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2783 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2784 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2785 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2786 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2787 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2788 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2789 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2790 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2791 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2792 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2793 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2794 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2795 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2796 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2797 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2798 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2799 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2800 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2801 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2802 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2803 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2804 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2805 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2806 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2807 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2808 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2809 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2810 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2811 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2812 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2813 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2814 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2815 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2816 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2817 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2818 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2819 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2820 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2821 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2822 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2823 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2824 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2825 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2826 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2827 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2828 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2829 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2830 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2831 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2832 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2833 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2834 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2835 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2836 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2837 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2838 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2839 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2840 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2841 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2842 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2843 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2844 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2845 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2846 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2847 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2848 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2849 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2850 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2851 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2852 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2853 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2854 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2855 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2856 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2857 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2858 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2859 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2860 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2861 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2862 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2863 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2864 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2865 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2866 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2867 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2868 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2869 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2870 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2871 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2872 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2873 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2874 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2875 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2876 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2877 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2878 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2879 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2880 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2881 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2882 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2883 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2884 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2885 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2886 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2887 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2888 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2889 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2890 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2891 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2892 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2893 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2894 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2895 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2896 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2897 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2898 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2899 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2900 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2901 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2902 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2903 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2904 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2905 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2906 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2907 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2908 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2909 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2910 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2911 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2912 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2913 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2914 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2915 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2916 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2917 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2918 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2919 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2920 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2921 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2922 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2923 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2924 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2925 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2926 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2927 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2928 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2929 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2930 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2931 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2932 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2933 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2934 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2935 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2936 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2937 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2938 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2939 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2940 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2941 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2942 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2943 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2944 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2945 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2946 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2947 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2948 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2949 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2950 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2951 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2952 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2953 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2954 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2955 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2956 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2957 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2958 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2959 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2960 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2961 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2962 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2963 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2964 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2965 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2966 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2967 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2968 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2969 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2970 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2971 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2972 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2973 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2974 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2975 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2976 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2977 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2978 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2979 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2980 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2981 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2982 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2983 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2984 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2985 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2986 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2987 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2988 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2989 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2990 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2991 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2992 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2993 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2994 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2995 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2996 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2997 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2998 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2999 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3000 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3001 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3002 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3003 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3004 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3005 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3006 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3007 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3008 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3009 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3010 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3011 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3012 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3013 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3014 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3015 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3016 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3017 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3018 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3019 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3020 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3021 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3022 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3023 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3024 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3025 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3026 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3027 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3028 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3029 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3030 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3031 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3032 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3033 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3034 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3035 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3036 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3037 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3038 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3039 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3040 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3041 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3042 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3043 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3044 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3045 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3046 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3047 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3048 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3049 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3050 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3051 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3052 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3053 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3054 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3055 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3056 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3057 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3058 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3059 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3060 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3061 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3062 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3063 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3064 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3065 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3066 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3067 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3068 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3069 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3070 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3071 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3072 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3073 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3074 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3075 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3076 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3077 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3078 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3079 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3080 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3081 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3082 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3083 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3084 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3085 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3086 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3087 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3088 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3089 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3090 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3091 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3092 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3093 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3094 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3095 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3096 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3097 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3098 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3099 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3100 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3102 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3105 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3106 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3107 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3108 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3109 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3110 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3112 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3114 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3115 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3116 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3117 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3119 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3120 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3121 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3122 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3123 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3125 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3126 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3127 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3128 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3129 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3130 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3131 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3132 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3133 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3134 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3136 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3138 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3140 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3142 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3143 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3144 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3145 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3147 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3148 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3149 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3150 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3151 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3152 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3154 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3155 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3156 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3157 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3158 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3160 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3161 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3162 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3164 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3165 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3166 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3167 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3168 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3169 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3170 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3171 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3172 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3173 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3174 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3175 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3177 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3179 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3181 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3182 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3183 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3184 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3185 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3186 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3187 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3188 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3189 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3190 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3191 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3192 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3193 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3195 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3196 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3197 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3198 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3199 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3200 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3201 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3202 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3203 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3204 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3205 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3206 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3207 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3208 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3209 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3210 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3211 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3212 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3213 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3214 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3215 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3220 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3221 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3222 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3223 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3224 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3225 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3226 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3227 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3228 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3229 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3231 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3233 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3237 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3238 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3240 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3244 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3247 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3248 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3250 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3251 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3252 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3254 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3255 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3256 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3257 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3258 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3259 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3260 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3261 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3262 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3263 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3264 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3265 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3266 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3267 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3268 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3269 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3270 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3271 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3272 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3273 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3274 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3275 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3276 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3277 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3278 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3279 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U3 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U4 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U6 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U9 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U3 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U4 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U6 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U9 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U3 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U4 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U5 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U3 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U4 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U5 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U3 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U4 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U5 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U3 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U4 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U5 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U3 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U4 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U5 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U3 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U4 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U6 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U9 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_shm_write_reg + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U3 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U4 + NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U5 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U6 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U7 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U8 + NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U9 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U10 + NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U11 + NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U12 + NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U13 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U14 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U15 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U16 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U17 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U18 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U19 + NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U20 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U21 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U22 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U23 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U24 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U25 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U26 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U27 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U28 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U29 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U30 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U31 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U32 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U33 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U34 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U39 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U40 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U41 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U46 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U47 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U48 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U49 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U50 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U51 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U52 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U53 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U54 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U55 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U56 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U57 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U58 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U59 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U60 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U61 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U62 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U63 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U64 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U65 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U66 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U67 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U68 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U69 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U70 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U71 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U72 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U73 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U74 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U75 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U76 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U77 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U78 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U79 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U80 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U81 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U82 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U83 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U84 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U85 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U86 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U87 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U88 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U89 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U90 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U91 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U92 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U93 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U94 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U95 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U96 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U97 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U98 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U99 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U100 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U101 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U102 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U103 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U105 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U106 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U107 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U113 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U114 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U116 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U117 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U123 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U125 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U126 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U129 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U136 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U137 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U140 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U147 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U150 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U155 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U156 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U165 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U167 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U175 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U177 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U183 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U184 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U185 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U186 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U187 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U188 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U190 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U191 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U192 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U193 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U194 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U195 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U196 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U197 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U198 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U200 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U201 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U202 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U203 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U209 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U212 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U215 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U217 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U220 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U221 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U223 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U229 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U232 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U248 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U249 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U258 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U273 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U275 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U279 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U282 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U292 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U296 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U299 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U307 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U309 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U310 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U312 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U313 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U315 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U316 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U318 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U319 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U323 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U324 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U326 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U327 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U330 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U332 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U333 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U334 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U336 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U339 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U340 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U341 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U342 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U344 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U345 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U346 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U347 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U352 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U353 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U354 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U355 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U357 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U360 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U361 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U363 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U364 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U366 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U370 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U372 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U373 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U376 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U379 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U382 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U386 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U387 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U388 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U389 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U390 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U391 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U392 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U393 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U395 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U396 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U398 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U399 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U400 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U401 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U402 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U403 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U404 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U405 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U407 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U409 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U411 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U412 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U414 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U419 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U421 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U426 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U427 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U429 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U430 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U431 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U433 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U434 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U435 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U437 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U440 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U443 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U444 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U445 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U446 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U449 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U450 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U452 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U455 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U457 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U460 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U463 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U466 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U467 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U468 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U469 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U471 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U472 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U473 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U474 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U475 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U476 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U477 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U478 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U479 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U480 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U481 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U482 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U483 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U484 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U485 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U486 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U487 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U488 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U489 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U490 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U491 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U492 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U493 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U494 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U495 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U496 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U497 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U498 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U499 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U500 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U501 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U502 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U503 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U504 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U505 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U506 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U507 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U508 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U509 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U511 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U512 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U513 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U514 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U515 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U516 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U517 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U518 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U519 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U520 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U521 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U522 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U523 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U524 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U525 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U526 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U527 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U528 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U529 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U530 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U531 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U532 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U533 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U534 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U535 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U536 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U537 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U538 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U539 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U540 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U541 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U542 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U543 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U544 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U545 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U546 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U547 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U548 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U549 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U550 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U551 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U552 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U553 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U554 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U555 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U556 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U557 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U558 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U559 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U560 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U561 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U562 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U563 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U564 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U565 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U566 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U567 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U568 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U569 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U570 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U571 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U572 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U573 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U574 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U575 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U576 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U577 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U578 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U579 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U580 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U581 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U582 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U583 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U585 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U586 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U587 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U588 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U590 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U591 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U593 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U594 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U595 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U596 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U598 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U599 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U600 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U601 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U602 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U603 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U604 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U605 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U606 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U607 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U608 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U610 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U611 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U612 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U613 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U614 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U615 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U616 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U617 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U618 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U619 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U620 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U621 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U622 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U623 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U624 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U625 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U626 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U627 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U628 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U629 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U630 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U631 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U632 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U634 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U636 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U637 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U638 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U639 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U640 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U641 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U642 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U643 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U644 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U645 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U646 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U647 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U648 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U649 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U650 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U651 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U652 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U653 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U654 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U655 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U656 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U657 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U658 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U659 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U660 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U661 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U662 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U663 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U664 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U665 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U666 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U667 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U671 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U672 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U674 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U675 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U677 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U678 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U680 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U681 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U683 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U684 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U685 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U686 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U687 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U690 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U692 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U693 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U695 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U696 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U697 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U698 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U700 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U701 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U703 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U704 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U705 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U707 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U708 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U710 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U712 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U713 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U715 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U716 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U718 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U719 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U721 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U722 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U724 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U725 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U726 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U727 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U728 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U729 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U730 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U731 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U733 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U734 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U736 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U737 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U738 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U739 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U740 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U742 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U743 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U744 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U745 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U747 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U748 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U750 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U751 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U752 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U753 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U754 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U755 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U756 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U759 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U760 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U761 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U762 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U763 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U764 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U765 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U766 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U767 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U768 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U769 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U770 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U771 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U772 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U773 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U774 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U776 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U777 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U779 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U780 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U782 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U783 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U785 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U786 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U788 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U789 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U790 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U791 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U793 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U794 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U796 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U797 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U798 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U800 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U801 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U802 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U804 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U805 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U806 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U807 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U808 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U809 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U810 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U811 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U812 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U813 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U814 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U815 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U816 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U817 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U818 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U819 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U820 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U821 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U823 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U824 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U825 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U827 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U828 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U829 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U830 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U831 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U832 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U833 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U834 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U835 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U836 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U838 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U839 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U840 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U841 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U842 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U843 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U844 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U845 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U846 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U847 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U848 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U849 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U850 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U851 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U852 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U853 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U856 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U857 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U858 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U859 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U861 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U862 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U864 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U865 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U866 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U867 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U868 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U870 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U871 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U872 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U873 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U874 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U876 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U877 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U878 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U880 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U881 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U882 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U884 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U885 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U887 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U888 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U889 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U890 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U892 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U893 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U894 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U895 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U896 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U897 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U899 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U900 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U903 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U904 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U905 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U906 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U907 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U908 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U910 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U911 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U912 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U914 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U915 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U916 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U918 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U919 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U921 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U922 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U924 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U925 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U926 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U927 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U928 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U929 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U931 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U932 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U934 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U935 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U936 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U937 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U938 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U939 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U940 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U941 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U942 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U943 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U944 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U945 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U946 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U947 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U948 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U949 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U950 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U951 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U952 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U953 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U954 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U955 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U957 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U958 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U959 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U960 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U961 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U962 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U963 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U964 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U966 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U967 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U968 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U969 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U970 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U972 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U973 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U975 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U977 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U978 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U980 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U981 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U982 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U983 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U984 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U986 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U987 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U988 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U989 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U990 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U991 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U992 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U993 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U994 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U995 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U997 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U998 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U999 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1001 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1004 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1005 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1007 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1008 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1009 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1010 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1011 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1012 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1013 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1014 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1015 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1017 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1018 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1019 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1020 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1021 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1023 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1024 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1025 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1026 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1027 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1028 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1029 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1030 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1031 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1032 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1033 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1034 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1035 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1036 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1037 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1038 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1039 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1040 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1041 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1042 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1043 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1045 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1046 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1047 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1048 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1049 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1050 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1051 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1052 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1053 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1054 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1055 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1056 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1057 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1058 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1060 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1061 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1062 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1063 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1064 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1065 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1066 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1067 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1068 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1069 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1070 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1071 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1072 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1073 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1074 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1075 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1076 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1077 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1078 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1080 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1081 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1082 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1083 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1084 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1086 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1087 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1088 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1089 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1090 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1091 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1094 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1095 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1097 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1098 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1099 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1112 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1123 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1126 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1209 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1212 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1215 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1218 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1220 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1221 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1223 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1229 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1232 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1248 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1249 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1251 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1252 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1254 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1257 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1275 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1280 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U1 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U2 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U3 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U5 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U5 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U6 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U8 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U5 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U8 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U7 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U8 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U5 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U8 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U5 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U8 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U5 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U8 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U7 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U8 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U5 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U8 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U2 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U3 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U5 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U10 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U11 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U13 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U14 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U16 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U19 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U20 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U22 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U26 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U27 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U28 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U29 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U30 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U31 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U32 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U33 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U34 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U35 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U36 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U37 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U38 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U39 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U40 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U41 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U42 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U43 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U44 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U45 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U46 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U47 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U48 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U49 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U3 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U4 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U5 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U6 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U7 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U8 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U9 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U10 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U11 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U12 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U13 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U14 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U15 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U16 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U17 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U18 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U19 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U20 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U21 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U22 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U23 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U24 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U25 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U26 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U27 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U28 BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U29 NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U30 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U31 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U32 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U33 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U34 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U35 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U36 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U37 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U38 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U39 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U40 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U41 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U42 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U43 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U44 AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U45 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U46 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U47 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U48 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U49 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U50 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U51 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U52 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U53 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U54 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U55 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U56 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U57 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U58 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U59 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U60 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U61 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U62 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U63 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U64 NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U65 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U66 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U67 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U68 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U69 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U70 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U71 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U72 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U73 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U74 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U75 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U76 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U77 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U78 OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U79 AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U80 OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U81 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U82 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U83 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U84 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U85 OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U86 AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U87 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U88 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U89 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U90 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U91 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U92 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U93 OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U94 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U95 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U96 AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U97 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U98 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U99 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U100 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U101 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U102 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U103 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U104 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U105 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U106 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U107 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U108 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U109 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U110 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U111 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U112 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U113 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U114 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U115 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U116 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U117 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U118 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U119 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U120 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U121 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U122 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U123 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U124 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U125 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U126 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U127 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U128 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U129 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U130 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U131 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U132 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U133 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U134 NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U135 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U136 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U137 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U138 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U139 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U140 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U141 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U142 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U143 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U144 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U145 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U146 AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U147 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U148 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U149 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U150 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U151 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U152 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U153 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U154 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U155 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U156 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U157 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U158 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U159 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U160 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U161 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U162 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U163 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U164 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U165 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U166 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U167 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U168 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U169 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U170 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U171 NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U172 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U173 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U174 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U175 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U176 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U177 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U178 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U179 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U180 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U181 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U182 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U183 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U184 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U185 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U186 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U187 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_rename_table_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_U1 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_csr_wrapper_U3 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_csr_wrapper_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U5 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_csr_wrapper_U6 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U7 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U10 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_csr_wrapper_U11 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_csr_wrapper_U12 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U13 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U2 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U3 + AND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U4 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U5 + NAND3XXB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U6 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U7 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U8 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U10 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U11 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U12 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U13 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U15 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U16 + NOR4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U17 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U18 + NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U19 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U20 + NAND4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U21 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U22 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U23 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U24 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U25 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U26 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U27 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U28 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U29 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U30 + NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U31 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_U32 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U33 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U34 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U35 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U36 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U37 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U38 + OR4_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U39 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U40 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U41 + NOR4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U42 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U44 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U45 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U46 + NAND4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U47 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U48 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U49 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U50 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U51 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U52 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_U53 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U54 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U55 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U56 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U57 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U58 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U59 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U60 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U61 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U62 + NAND4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_U63 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U64 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U65 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U66 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U67 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U68 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U69 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U70 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U71 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U72 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U73 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U74 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U75 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U76 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U77 + AO21A1AI2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U78 + NAND4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U79 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U80 + NAND3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U81 + NOR4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U82 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U83 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U84 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U85 + OR4_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U86 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U87 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U88 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U89 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U90 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U91 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U92 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U93 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U94 + OR4_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U95 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U96 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U97 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U98 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U99 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U100 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U101 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_U102 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U103 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U104 + NAND4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U105 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U106 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U107 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U108 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U109 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U110 + OR4_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U111 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U112 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U113 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U114 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U115 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U116 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U117 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U118 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U119 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U120 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U121 + OR4_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U122 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U123 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U124 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U125 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U126 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U127 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U128 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U129 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U130 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U131 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U132 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U133 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U134 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U135 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U136 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U137 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U138 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U139 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U140 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U141 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U142 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U143 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U144 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U145 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U146 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U147 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U148 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U149 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U150 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U151 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U152 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U153 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U154 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U155 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U156 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U157 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U158 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U159 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U160 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U161 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U162 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U163 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U164 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U165 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U166 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U167 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U168 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U169 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U170 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U171 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U172 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U173 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U174 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U175 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U176 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U177 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U178 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U179 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U180 + NAND4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U181 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U182 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U183 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U184 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U185 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U186 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U187 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U188 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U189 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U190 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U191 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U192 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U193 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U194 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U195 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U196 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U197 + AND3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U198 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U199 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U200 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U201 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U202 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U203 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U204 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U205 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U206 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U207 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U208 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U209 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U210 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U211 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U212 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U213 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U214 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U215 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U216 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U217 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U218 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U219 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U220 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U221 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U222 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U223 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U224 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U225 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U226 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U227 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U228 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U229 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U230 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U231 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U232 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U233 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U234 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U235 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U236 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U237 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U238 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U239 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U240 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U241 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U242 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U243 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U244 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U245 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U246 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U247 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U248 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U249 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U250 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U251 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U252 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U253 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U254 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U255 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U256 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U257 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U258 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U259 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U260 + OA1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U261 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_U262 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_U263 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U264 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U265 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U266 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U267 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_add_x_3_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U33 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_add_x_4_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U32 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_choose_alu_result_U3 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_choose_alu_result_U4 + OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_choose_alu_result_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_choose_alu_result_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_choose_alu_result_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_44J8_122_6278_U33 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U266 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U267 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U268 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U269 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U270 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U271 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U272 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U273 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U274 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U275 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U276 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U277 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U278 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U279 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U280 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U281 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U282 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U283 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U284 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U285 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U286 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U287 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U288 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U289 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U290 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U291 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U292 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U293 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U294 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U295 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U296 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U297 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U298 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U299 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U300 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U301 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U302 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U303 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U304 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U305 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U306 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U307 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U308 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U309 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U310 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U311 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U312 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U313 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U314 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U315 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U316 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U317 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U318 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U319 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U320 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U321 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U322 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U323 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U324 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U325 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U326 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U327 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U328 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U355 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U356 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U357 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U358 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U359 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U360 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U361 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U362 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U364 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U365 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U366 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U367 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U369 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U370 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U371 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U372 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U373 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U374 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U375 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U376 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U377 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U378 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U380 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U381 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U382 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U383 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U384 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U386 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U387 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U388 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U389 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U390 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U391 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U392 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U393 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U394 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U395 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U396 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U397 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U399 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U400 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U401 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U402 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U403 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U404 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U406 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U407 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U408 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U409 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U410 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U411 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U412 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U413 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U414 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U415 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U416 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U417 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U418 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U419 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U421 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U422 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U423 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U424 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U425 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U426 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U427 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U429 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U430 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U431 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U432 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U433 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U434 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U435 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U436 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U437 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U438 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U439 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U440 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U441 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U442 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U443 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U444 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U446 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U447 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U448 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U449 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U450 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U451 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U452 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U453 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U455 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U456 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U457 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U458 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U459 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U460 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U461 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U462 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U463 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U464 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U465 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U466 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U467 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U468 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U469 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U470 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U471 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U472 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U474 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U475 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U476 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U477 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U478 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U479 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U480 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U481 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U482 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U484 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U485 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U486 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U487 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U488 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U489 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U490 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U491 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U492 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U494 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U495 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U496 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U497 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U498 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U499 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U500 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U501 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U502 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U503 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U504 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U505 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U506 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U507 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U508 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U509 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U510 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U511 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U512 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U513 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U514 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U515 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U516 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U517 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U518 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U519 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U520 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U521 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U522 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U523 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U524 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U525 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U526 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U527 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U528 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U529 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U530 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U531 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U532 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U533 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U534 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U535 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U536 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U537 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U538 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U539 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U540 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U541 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U542 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U543 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U544 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U545 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U546 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U547 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U548 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U549 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U550 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U551 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U552 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U553 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U554 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U555 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U556 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U557 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U558 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U559 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U560 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U561 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U562 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U563 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U564 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U565 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U566 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U567 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U568 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U569 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U570 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U571 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U572 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U573 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U574 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U575 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U576 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U577 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U578 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U579 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U580 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U581 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U582 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U583 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U584 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U585 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U586 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U587 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U588 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U589 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U590 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U591 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U592 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U593 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U594 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U595 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U596 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U597 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U598 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U599 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U600 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U601 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U602 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U603 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U604 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U605 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U606 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U607 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U608 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U609 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U610 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U611 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U612 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U613 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U614 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U615 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U616 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U617 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U618 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U619 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U620 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U621 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U622 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U623 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U624 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U625 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U626 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U627 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U628 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U629 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U630 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U631 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U632 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U633 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U634 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U635 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U636 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U637 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U638 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U639 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U640 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U641 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U642 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U643 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U644 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U645 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U646 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U647 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U648 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U649 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U650 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U651 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U652 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U653 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U654 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U655 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U656 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U657 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U658 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U659 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U660 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U661 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U662 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U663 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U664 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2323 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2324 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2325 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2326 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2327 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2328 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2329 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2330 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2333 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2335 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2340 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2343 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2350 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_DP_OP_47J8_126_5279_U2354 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U4 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U6 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U7 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U8 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U9 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U10 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13 + NOR3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U16 + OAI2XB1_X0P7M_A12TUL_C35 + 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0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1731 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1732 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1733 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1734 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1735 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1736 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1737 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1752 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1753 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1754 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1755 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1756 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1757 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1758 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1773 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1774 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1775 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1776 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1777 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1778 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1779 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1780 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1781 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1782 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1783 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1784 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1785 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1786 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1787 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1788 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1789 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1790 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1791 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1792 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1793 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1794 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1795 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1796 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1797 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1798 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1799 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1800 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1801 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1802 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1803 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1804 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1805 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1806 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1807 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1843 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1844 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1845 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1846 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1847 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1848 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1849 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1850 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1851 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1852 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1853 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1854 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1855 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U1856 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2109 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2110 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2111 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2112 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2113 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2114 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2115 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2116 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2117 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2118 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2119 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2120 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2121 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2122 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2123 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2124 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2125 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2126 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2127 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2128 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2129 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2130 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2131 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2132 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2133 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2134 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2135 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2136 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2137 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2138 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2139 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2140 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2141 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2142 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2143 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2144 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2145 + INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2146 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2147 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2148 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2149 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2150 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2151 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2152 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2153 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2154 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2155 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2156 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2157 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2158 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2159 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2160 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2161 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2162 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2163 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2164 + MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2165 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2166 + OAI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2167 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2168 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2169 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2170 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2171 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2172 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2173 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2174 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2175 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2176 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2177 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2178 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2179 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2180 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2181 + AOI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2182 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2183 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2184 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U2185 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3320 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3321 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3322 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3323 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3324 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3325 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3326 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3788 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3789 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3790 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3791 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3792 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3793 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3794 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3795 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3796 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3797 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3798 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3799 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3800 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3801 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3802 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3803 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3804 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3805 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3806 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3807 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3808 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5164 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5165 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5166 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5167 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5168 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5169 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5170 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5340 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5341 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5342 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5343 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5344 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5345 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12770 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12771 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12772 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12773 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12774 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12775 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12776 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14080 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14081 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14082 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14083 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14084 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14085 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14086 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14087 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14088 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14089 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14090 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14091 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14092 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14093 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14094 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14095 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14096 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14097 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14098 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14099 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14100 + 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+vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14107 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14108 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14109 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14111 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14112 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14113 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14114 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14115 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14116 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14117 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14118 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14121 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14122 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14123 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14124 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14125 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14127 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14128 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14129 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14131 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14132 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14133 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14134 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14138 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14145 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14146 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14147 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14148 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14149 + OR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14150 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14152 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14153 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14154 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14162 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14163 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14164 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14165 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14166 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14167 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14168 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15901 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15902 + AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15903 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15904 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15905 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15906 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15907 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15921 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15922 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15923 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15924 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15925 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15926 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15927 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15928 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15929 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15930 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15931 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15932 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15933 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15934 + INV_X1M_A12TUL_C35 + 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+ AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17981 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17982 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17983 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17984 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17985 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17986 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+ INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18125 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18126 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18127 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18128 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18129 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18130 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18131 + 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+ INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18139 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18140 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18141 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18142 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18143 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18144 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18152 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18153 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18154 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18155 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18156 + OAI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18157 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18158 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19603 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19604 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19605 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19606 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19607 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19608 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19609 + 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+vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19637 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19638 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19639 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19640 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19641 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19642 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19643 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19644 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19645 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19646 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19647 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19648 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19649 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19650 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19651 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19652 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19653 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19654 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19655 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19656 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19657 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19658 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19659 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19660 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19661 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19662 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19663 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19664 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19665 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19666 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19667 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19668 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19669 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19670 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19671 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19672 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19673 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19674 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19675 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19676 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19677 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19678 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19679 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19680 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19681 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19682 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19683 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19684 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19685 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19686 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19687 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19688 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19689 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19690 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19691 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19692 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19693 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19694 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19695 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19696 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19697 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19698 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19699 + NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19700 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19701 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19702 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19703 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19704 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19705 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19706 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19707 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19708 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19709 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19710 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19711 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19712 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19713 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19714 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19715 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19716 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19717 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19718 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19719 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20721 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20722 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20723 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20724 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20725 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20726 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20727 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20728 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20729 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20730 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20731 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20732 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20733 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20748 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20749 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20750 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20751 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20752 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20753 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20754 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20755 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20756 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20757 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20758 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20759 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20760 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20761 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26906 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26907 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26908 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26909 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26910 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26911 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_44J8_122_6278_U33 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U266 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U267 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U268 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U269 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U270 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U271 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U272 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U273 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U274 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U275 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U276 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U277 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U278 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U279 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U280 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U281 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U282 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U283 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U284 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U285 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U286 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U287 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U288 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U289 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U290 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U291 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U292 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U293 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U294 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U295 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U296 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U297 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U298 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U299 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U300 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U301 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U302 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U303 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U304 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U305 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U306 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U307 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U308 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U309 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U310 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U311 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U312 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U313 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U314 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U315 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U316 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U317 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U318 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U319 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U320 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U321 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U322 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U323 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U324 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U325 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U326 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U327 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U328 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U355 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U356 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U357 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U358 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U359 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U360 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U361 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U362 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U364 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U365 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U366 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U367 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U369 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U370 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U371 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U372 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U373 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U374 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U375 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U376 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U377 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U378 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U380 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U381 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U382 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U383 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U384 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U386 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U387 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U388 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U389 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U390 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U391 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U392 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U393 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U394 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U395 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U396 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U397 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U399 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U400 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U401 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U402 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U403 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U404 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U406 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U407 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U408 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U409 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U410 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U411 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U412 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U413 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U414 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U415 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U416 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U417 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U418 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U419 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U421 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U422 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U423 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U424 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U425 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U426 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U427 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U429 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U430 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U431 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U432 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U433 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U434 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U435 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U436 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U437 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U438 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U439 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U440 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U441 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U442 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U443 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U444 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U446 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U447 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U448 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U449 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U450 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U451 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U452 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U453 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U455 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U456 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U457 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U458 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U459 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U460 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U461 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U462 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U463 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U464 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U465 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U466 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U467 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U468 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U469 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U470 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U471 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U472 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U474 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U475 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U476 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U477 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U478 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U479 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U480 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U481 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U482 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U484 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U485 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U486 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U487 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U488 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U489 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U490 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U491 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U492 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U494 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U495 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U496 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U497 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U498 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U499 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U500 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U501 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U502 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U503 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U504 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U505 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U506 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U507 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U508 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U509 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U510 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U511 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U512 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U513 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U514 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U515 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U516 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U517 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U518 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U519 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U520 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U521 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U522 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U523 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U524 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U525 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U526 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U527 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U528 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U529 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U530 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U531 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U532 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U533 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U534 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U535 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U536 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U537 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U538 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U539 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U540 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U541 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U542 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U543 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U544 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U545 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U546 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U547 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U548 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U549 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U550 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U551 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U552 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U553 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U554 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U555 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U556 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U557 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U558 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U559 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U560 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U561 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U562 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U563 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U564 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U565 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U566 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U567 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U568 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U569 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U570 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U571 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U572 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U573 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U574 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U575 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U576 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U577 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U578 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U579 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U580 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U581 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U582 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U583 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U584 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U585 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U586 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U587 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U588 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U589 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U590 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U591 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U592 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U593 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U594 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U595 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U596 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U597 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U598 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U599 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U600 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U601 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U602 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U603 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U604 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U605 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U606 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U607 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U608 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U609 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U610 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U611 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U612 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U613 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U614 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U615 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U616 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U617 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U618 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U619 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U620 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U621 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U622 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U623 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U624 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U625 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U626 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U627 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U628 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U629 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U630 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U631 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U632 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U633 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U634 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U635 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U636 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U637 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U638 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U639 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U640 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U641 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U642 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U643 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U644 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U645 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U646 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U647 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U648 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U649 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U650 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U651 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U652 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U653 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U654 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U655 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U656 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U657 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U658 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U659 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U660 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U661 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U662 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U663 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U664 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2323 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2324 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2325 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2326 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2327 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2328 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2329 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2330 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2333 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2335 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2340 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2343 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2350 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_DP_OP_47J8_126_5279_U2354 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U3 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U7 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U8 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U15 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U16 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U20 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U22 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U23 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U24 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U25 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U26 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U27 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U29 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U30 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U32 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U35 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U38 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U39 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U40 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U41 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U42 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U43 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U44 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U45 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U46 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U47 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U48 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U49 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U50 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U51 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U52 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U53 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U54 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U55 + 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+ NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1281 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1282 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1283 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1284 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1285 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1286 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1287 + 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1399 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1400 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1401 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1402 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1403 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1404 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1405 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1448 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1449 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1450 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1451 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1452 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1453 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1454 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 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0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1609 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1610 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1611 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1612 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1613 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1614 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1615 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1616 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1617 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1618 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1619 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1620 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1621 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1622 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1623 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1624 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1625 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1626 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1627 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1628 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1629 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1644 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1645 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1646 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1647 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1648 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1649 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1650 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1679 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1680 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1681 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1682 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1683 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1684 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1685 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1686 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1687 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1688 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1689 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1690 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1691 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1692 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1693 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1694 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1695 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1696 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1697 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1698 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1699 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1700 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1701 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1702 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1703 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1704 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1705 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1706 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1707 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1708 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1709 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1710 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1711 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1712 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1713 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1728 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1729 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1730 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1731 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1732 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1733 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1734 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1742 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1743 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1744 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1745 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1746 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1747 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1748 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1749 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1750 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1751 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1752 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1753 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1754 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1755 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1756 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1757 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1758 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1759 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1760 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1761 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1762 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1763 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1764 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1765 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1766 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1767 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1768 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1769 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1770 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1771 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1772 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1773 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1774 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1775 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1776 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1777 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1778 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1779 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1780 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1781 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1782 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1783 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1784 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1785 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1786 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1787 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1788 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1789 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1790 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1791 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1792 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1793 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1794 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1795 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1796 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1797 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1798 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1799 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1800 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1801 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1802 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1803 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1804 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1840 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1841 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1842 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1843 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1844 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1845 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1846 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1847 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1848 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1849 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1850 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1851 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1852 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1853 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1854 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1855 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1856 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1857 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1858 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1859 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1860 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1861 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1862 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1863 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1864 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1865 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1866 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1867 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1868 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1869 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1870 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1871 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1872 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1873 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1874 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1875 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1876 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1877 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1878 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1879 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1880 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1881 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1931 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1932 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1933 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1934 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1935 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1936 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1937 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1938 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1939 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1940 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1941 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1942 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1943 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U1944 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2001 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2002 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2003 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2004 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2005 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2006 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2007 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2064 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2065 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2066 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2067 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2068 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2069 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2070 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2078 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2079 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2080 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2081 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2082 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2083 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2084 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2092 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2093 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2094 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2095 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2096 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2097 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2098 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2106 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2107 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2108 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2109 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2110 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2111 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2112 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2113 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2114 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2115 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2116 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2117 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2118 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2119 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2120 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2121 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2122 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2123 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2124 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2125 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2126 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2190 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2191 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2192 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2193 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2194 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2195 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2196 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2197 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2198 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2199 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2200 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2201 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2202 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2203 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2512 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2513 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2514 + OAI21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2515 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2516 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2517 + OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2518 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2519 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2520 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2521 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2522 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2523 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2524 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2525 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2540 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2541 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2542 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2543 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2544 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2545 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2546 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2554 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2555 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2556 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2557 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2558 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2559 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2560 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2561 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2562 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2563 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2564 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2565 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2566 + MXT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2567 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2568 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2569 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2570 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2572 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2573 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2574 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2575 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2576 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2577 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2578 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2579 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2580 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U2581 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4644 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4645 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4646 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4647 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4648 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4649 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4650 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4651 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4652 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4653 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4654 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4655 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4656 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4657 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4658 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4659 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4660 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4661 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4662 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4663 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4664 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4867 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4868 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4869 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4870 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4871 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4872 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U4873 + NOR2_X1M_A12TUL_C35 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6521 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6524 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6525 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6526 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6527 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10770 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10771 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10772 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10773 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10774 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10775 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10776 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10777 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10778 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10779 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10780 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10781 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10782 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10783 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10784 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10785 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10786 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10787 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10788 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10789 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10790 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10791 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10792 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10793 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10794 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10795 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10796 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10797 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10798 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10799 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10800 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10801 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10802 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10803 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10804 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10805 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10806 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10807 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10808 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10809 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10810 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10811 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10812 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10813 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10814 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10815 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10816 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10817 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10818 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10819 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10820 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10821 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10822 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10823 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U10824 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12001 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12002 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12003 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12004 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12005 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12006 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12062 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12063 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12064 + OA1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12065 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12066 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12067 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12068 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12069 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12070 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12071 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12072 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12073 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12074 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12075 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12076 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12077 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12078 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12079 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12080 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12081 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12082 + AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12083 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12084 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12085 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12086 + OA211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12087 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12088 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12089 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12090 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12091 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12092 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12093 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12094 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12095 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12096 + 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+ NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12104 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12105 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12106 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12107 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12108 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12109 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12110 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12111 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12112 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12114 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12115 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12116 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12124 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12125 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12126 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12127 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12128 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12129 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12130 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12131 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12132 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12133 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12134 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12135 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12136 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12137 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12568 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12569 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12570 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12571 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12572 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12573 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12574 + NAND2_X1B_A12TUL_C35 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12609 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12610 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12614 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12615 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12625 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12626 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12627 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12628 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12629 + AOI21_X1P4M_A12TUL_C35 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13000 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13001 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13002 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13003 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13004 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13005 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13006 + NAND2_X1B_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13014 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13015 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13016 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13017 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13018 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13019 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13020 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13021 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13022 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13023 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13024 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13025 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13026 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13027 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13028 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13029 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13030 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13031 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13032 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13033 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13034 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13035 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13036 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13037 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13038 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13039 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13040 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13041 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13042 + NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13043 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13044 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13045 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13046 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13047 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13048 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13049 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13050 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13051 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13052 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13053 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13054 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13055 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13056 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13057 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13058 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13059 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13060 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13061 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13062 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13063 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13064 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13065 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13066 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13067 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13068 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13069 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13070 + AO21A1AI2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13071 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13072 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13073 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13074 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13075 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13076 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13077 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13078 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13079 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13080 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13081 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13082 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13083 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13084 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13085 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13086 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13087 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13088 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13089 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13090 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13091 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13092 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13093 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13094 + AO21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13095 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13096 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13097 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13098 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13099 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13101 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13102 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13103 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13104 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13105 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13106 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13107 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13108 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13109 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13110 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13111 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13112 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13113 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13114 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13115 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13116 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13117 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13118 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13119 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13120 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13121 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13122 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13123 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13145 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13146 + NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13147 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13148 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13150 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13151 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13152 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13153 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13154 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13155 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13156 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13157 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13158 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13159 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13160 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13161 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13162 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13164 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13165 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13166 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13167 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13168 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13169 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13170 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13171 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13172 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13173 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13174 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13176 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13179 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13180 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13181 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13182 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13183 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13186 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13187 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13188 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13189 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13190 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13191 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13192 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13194 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13195 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13196 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13197 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13198 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13199 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13200 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13201 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13202 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13203 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13205 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13206 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13214 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13215 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13216 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13217 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13218 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13219 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13220 + AOI21_X2M_A12TUL_C35 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13304 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13305 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13306 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13307 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13308 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13309 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13310 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13333 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13334 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13335 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13336 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13338 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13339 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13340 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13341 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13342 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13343 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13344 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13345 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13346 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13347 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13348 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13349 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13350 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13351 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13352 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13353 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13354 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13355 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13356 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13357 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13358 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13359 + AO1B2_X3M_A12TUL_C35 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13581 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13582 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13583 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13584 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13585 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13586 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13587 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13725 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13726 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13727 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13728 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13729 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13730 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13731 + AOI21_X1M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13760 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13761 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13762 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13763 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13764 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13765 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13766 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14240 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14241 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14243 + MXT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14244 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14245 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U14246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17304 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17305 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17306 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17307 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17308 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17309 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17310 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17311 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17312 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17313 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17314 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17315 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17316 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17317 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17318 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17319 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17320 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17321 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17322 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17323 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17338 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17339 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17340 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17341 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17342 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17343 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17344 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17345 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17346 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17347 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17348 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17349 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17350 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17351 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17352 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17353 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17354 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17355 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17356 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17357 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17358 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17359 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17360 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17361 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17362 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17363 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17364 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17365 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17366 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17367 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17368 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17369 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17370 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17371 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17372 + 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+ NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17380 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17381 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17382 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17383 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17384 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17385 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17770 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17771 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17772 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17773 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17774 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17775 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U17776 + AOI21_X2M_A12TUL_C35 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18052 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18053 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18054 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18055 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18056 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18057 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18058 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18059 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18060 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18061 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18062 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18063 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18064 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18065 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18100 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18101 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18102 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18103 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18104 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18105 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18106 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18707 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18708 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18709 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18710 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18711 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18712 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18713 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18714 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18715 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18716 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18717 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18718 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18719 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18720 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18721 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18722 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18723 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18724 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18725 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18726 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18727 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18728 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18729 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18730 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18731 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18732 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18733 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18734 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18735 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18736 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18737 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18738 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18739 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18740 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18741 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18742 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18743 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18744 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18745 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18746 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18747 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18748 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18749 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18750 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18751 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18752 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18753 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18754 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18755 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18756 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18757 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18758 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18759 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18760 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18761 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18762 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18763 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18764 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18765 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18766 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18767 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18768 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18769 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18770 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18771 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18772 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18773 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18774 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U18775 + XOR2_X1M_A12TUL_C35 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19664 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19665 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19666 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19667 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19668 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19669 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19670 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19671 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19672 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19673 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19674 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19675 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19676 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19677 + OAI21_X3M_A12TUL_C35 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_44J8_122_6278_U33 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U266 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U267 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U268 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U269 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U270 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U271 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U272 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U273 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U274 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U275 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U276 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U277 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U278 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U279 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U280 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U281 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U282 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U283 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U284 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U285 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U286 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U287 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U288 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U289 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U290 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U291 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U292 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U293 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U294 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U295 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U296 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U297 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U298 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U299 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U300 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U301 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U302 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U303 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U304 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U305 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U306 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U307 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U308 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U309 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U310 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U311 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U312 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U313 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U314 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U315 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U316 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U317 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U318 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U319 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U320 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U321 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U322 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U323 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U324 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U325 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U326 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U327 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U328 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U355 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U356 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U357 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U358 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U359 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U360 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U361 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U362 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U364 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U365 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U366 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U367 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U369 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U370 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U371 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U372 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U373 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U374 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U375 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U376 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U377 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U378 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U380 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U381 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U382 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U383 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U384 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U386 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U387 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U388 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U389 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U390 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U391 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U392 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U393 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U394 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U395 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U396 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U397 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U399 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U400 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U401 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U402 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U403 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U404 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U406 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U407 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U408 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U409 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U410 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U411 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U412 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U413 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U414 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U415 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U416 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U417 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U418 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U419 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U421 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U422 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U423 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U424 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U425 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U426 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U427 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U429 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U430 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U431 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U432 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U433 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U434 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U435 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U436 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U437 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U438 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U439 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U440 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U441 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U442 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U443 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U444 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U446 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U447 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U448 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U449 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U450 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U451 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U452 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U453 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U455 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U456 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U457 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U458 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U459 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U460 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U461 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U462 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U463 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U464 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U465 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U466 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U467 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U468 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U469 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U470 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U471 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U472 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U474 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U475 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U476 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U477 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U478 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U479 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U480 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U481 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U482 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U484 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U485 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U486 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U487 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U488 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U489 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U490 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U491 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U492 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U494 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U495 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U496 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U497 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U498 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U499 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U500 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U501 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U502 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U503 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U504 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U505 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U506 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U507 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U508 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U509 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U510 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U511 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U512 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U513 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U514 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U515 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U516 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U517 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U518 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U519 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U520 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U521 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U522 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U523 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U524 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U525 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U526 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U527 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U528 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U529 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U530 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U531 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U532 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U533 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U534 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U535 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U536 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U537 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U538 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U539 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U540 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U541 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U542 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U543 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U544 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U545 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U546 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U547 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U548 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U549 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U550 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U551 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U552 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U553 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U554 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U555 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U556 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U557 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U558 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U559 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U560 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U561 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U562 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U563 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U564 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U565 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U566 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U567 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U568 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U569 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U570 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U571 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U572 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U573 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U574 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U575 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U576 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U577 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U578 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U579 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U580 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U581 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U582 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U583 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U584 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U585 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U586 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U587 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U588 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U589 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U590 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U591 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U592 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U593 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U594 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U595 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U596 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U597 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U598 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U599 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U600 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U601 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U602 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U603 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U604 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U605 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U606 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U607 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U608 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U609 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U610 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U611 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U612 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U613 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U614 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U615 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U616 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U617 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U618 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U619 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U620 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U621 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U622 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U623 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U624 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U625 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U626 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U627 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U628 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U629 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U630 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U631 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U632 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U633 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U634 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U635 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U636 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U637 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U638 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U639 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U640 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U641 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U642 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U643 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U644 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U645 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U646 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U647 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U648 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U649 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U650 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U651 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U652 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U653 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U654 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U655 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U656 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U657 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U658 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U659 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U660 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U661 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U662 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U663 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U664 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2323 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2324 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2325 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2326 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2327 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2328 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2329 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2330 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2333 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2335 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2340 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2343 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2350 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_DP_OP_47J8_126_5279_U2354 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U4 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U5 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U8 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1001 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1002 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1003 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1004 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1005 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1006 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1007 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1008 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1009 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1010 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1011 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1012 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1013 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1014 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1015 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1016 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1017 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1018 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1019 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1020 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1021 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1022 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1023 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1024 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1025 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1026 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1027 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1028 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1029 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1030 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1031 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1032 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1033 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1034 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1035 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1036 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1037 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1038 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1039 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1040 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1041 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1042 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1043 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1044 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1045 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1046 + MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1047 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1048 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1049 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1050 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1051 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1052 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1053 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1054 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1055 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1056 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1057 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1058 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1059 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1060 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1061 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1062 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1063 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1064 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1065 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1066 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1067 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1068 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1069 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1070 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1071 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1072 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1073 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1074 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1075 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1076 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1077 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1078 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1079 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1080 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1081 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1082 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1083 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1084 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1085 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1086 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1087 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1088 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1089 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1090 + OA21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1091 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1092 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1093 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1094 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1095 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1096 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1097 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1098 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1099 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1100 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1101 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1102 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1103 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1104 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1105 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1106 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1107 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1108 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1109 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1110 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1111 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1112 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1113 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1114 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1115 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1116 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1117 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1118 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1119 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1120 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1121 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1122 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1123 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1124 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1125 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1126 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1127 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1128 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1129 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1130 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1131 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1132 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1133 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1134 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1135 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1136 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1137 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1138 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1139 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1140 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1141 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1142 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1143 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1144 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1145 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1146 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1147 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1148 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1149 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1150 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1151 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1152 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1153 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1154 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1155 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1156 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1157 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1158 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1159 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1160 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1161 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1162 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1163 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1164 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1165 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1166 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1167 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1168 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1169 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1170 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1171 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1172 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1173 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1174 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1175 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1176 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1177 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1178 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1179 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1180 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1181 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1182 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1190 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1191 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1192 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1193 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1194 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1195 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1196 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1197 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1198 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1199 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1200 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1201 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1202 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1203 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1211 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1212 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1213 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1214 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1215 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1216 + OA21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1217 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1218 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1219 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1220 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1221 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1222 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1223 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1224 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1225 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1226 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1227 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1228 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1229 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1230 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1232 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1233 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1234 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1235 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1236 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1237 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1238 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1239 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1240 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1241 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1242 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1243 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1244 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1245 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1246 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1247 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1248 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1249 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1250 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1251 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1252 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1253 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1254 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1255 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1256 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1257 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1258 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1259 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1260 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1261 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1262 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1263 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1264 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1265 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1266 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1274 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1275 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1276 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1277 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1278 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1279 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1280 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1302 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1303 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1304 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1305 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1306 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1307 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1308 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1316 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1317 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1318 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1319 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1320 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1321 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1322 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1323 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1324 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1325 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1326 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1327 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1328 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1329 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1330 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1331 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1332 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1333 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1334 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1335 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1336 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1337 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1338 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1339 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1340 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1341 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1342 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1343 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1344 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1345 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1346 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1347 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1348 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1349 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1350 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1351 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1352 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1353 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1354 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1355 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1356 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1357 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1358 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1359 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1360 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1361 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1362 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1363 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1364 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1365 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1366 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1367 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1368 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1369 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1370 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1371 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1372 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1373 + MXT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1374 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1375 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1376 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1377 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1378 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1379 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1380 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1381 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1382 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1383 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1384 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1385 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1386 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1387 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1388 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1389 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1390 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1391 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1392 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1393 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1394 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1395 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1396 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1397 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1398 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1399 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1400 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1401 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1402 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1403 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1404 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1405 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1406 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1407 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1408 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1409 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1410 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1411 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1412 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1413 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1414 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1415 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1416 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1417 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1418 + MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1419 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1420 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1484 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1485 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1486 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1487 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1488 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1489 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1490 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1512 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1513 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1514 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1515 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1516 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1517 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1518 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1519 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1520 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1521 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1522 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1523 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1524 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1525 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1540 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1541 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1542 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1543 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1544 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1545 + OR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1546 + MXT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1554 + MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1555 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1556 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1557 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1558 + OA21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1559 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1560 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1561 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1562 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1563 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1564 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1565 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1566 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1567 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1568 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1569 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1570 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1571 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1572 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1573 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1574 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1575 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1576 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1577 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1578 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1579 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1580 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1581 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1582 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1583 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1584 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1585 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1586 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1587 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1588 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1589 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1590 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1591 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1592 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1593 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1594 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1595 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1596 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1597 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1598 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1599 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1600 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1601 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1602 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1603 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1604 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1605 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1606 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1607 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1608 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1609 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1610 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1611 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1612 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1613 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1614 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1615 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1616 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1617 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1618 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1619 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1620 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1621 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1622 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1623 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1624 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1625 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1626 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1627 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1628 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1629 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1630 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1631 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1632 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1633 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1634 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1635 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1636 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1637 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1638 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1639 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1640 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1641 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1642 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1643 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1644 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1645 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1646 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1647 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1648 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1649 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1650 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1651 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1652 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1653 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1654 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1655 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1656 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1657 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1658 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1659 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1660 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1661 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1662 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1663 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1664 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1665 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1666 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1667 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1668 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1669 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1670 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1671 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1672 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1680 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1681 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1682 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1683 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1684 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1685 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1686 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1701 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1702 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1703 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1704 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1705 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1706 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1707 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1708 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1709 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1710 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1711 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1712 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1713 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1714 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1715 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1716 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1717 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1718 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1719 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1720 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1721 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1722 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1723 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1724 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1725 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1726 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1727 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1728 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1729 + MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1730 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1731 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1732 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1733 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1734 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U1735 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2184 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2185 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2186 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2187 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2188 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2189 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U2190 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3203 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3205 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3206 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3207 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3208 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3209 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3210 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3211 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3213 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3214 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3215 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3216 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3224 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3226 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3227 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3228 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3229 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3230 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3232 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3233 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3234 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3235 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3236 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3238 + MXT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3239 + MXT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3240 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3241 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3242 + MXT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3243 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3244 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3245 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3246 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3247 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3248 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3249 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3250 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3251 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3252 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3253 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3254 + MXT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3255 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3256 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3257 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3280 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3281 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3282 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3283 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3284 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3285 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3286 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3846 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3847 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3848 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3849 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3850 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3851 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3852 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3874 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3875 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3876 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3877 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3878 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3879 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3880 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3881 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3882 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3883 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3884 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3885 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3886 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3887 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3888 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3889 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3890 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3891 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3892 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3893 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3894 + 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XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3916 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3917 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3918 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3919 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3920 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3921 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3922 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3923 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3924 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3925 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3926 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3927 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3928 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U3929 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6379 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6381 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6382 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6383 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6385 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6897 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6898 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6899 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6900 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6901 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6903 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7078 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7079 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7080 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7081 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7082 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7083 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7084 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7085 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7086 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7087 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7088 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7089 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7090 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7091 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7092 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7093 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7094 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7095 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7096 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7097 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7098 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7099 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7101 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7102 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7103 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7107 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7108 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7109 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7110 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7111 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7112 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7114 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7116 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7117 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7119 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7120 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7121 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7122 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7123 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7125 + AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7126 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7127 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7129 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7130 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7131 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7132 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7133 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7137 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7138 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7139 + XNOR2_X0P5M_A12TUL_C35 + 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7620 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7621 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7622 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7623 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7624 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7625 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7626 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7634 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7635 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7636 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7637 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7638 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7639 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7640 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7641 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7642 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7643 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7645 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7647 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7648 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7649 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7650 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7651 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7652 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7653 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7654 + INV_X0P6B_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7662 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7663 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7664 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7665 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7666 + OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7667 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U7668 + INV_X0P6B_A12TUL_C35 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9820 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9821 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9822 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9823 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9824 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9825 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9826 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10089 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10090 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10091 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10092 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10093 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10094 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10095 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10096 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10097 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10098 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10099 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10100 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10102 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10116 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10118 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10119 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10120 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10121 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10123 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10124 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10126 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10127 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10128 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10129 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10137 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10138 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10139 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10140 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10141 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10142 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10143 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10144 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10145 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10147 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10148 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10149 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10418 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10420 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10423 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10424 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10425 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10426 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10428 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10429 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10430 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10431 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10432 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10433 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10434 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10435 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10436 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10437 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10445 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10446 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10447 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10448 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10449 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10450 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10451 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10452 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10453 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10454 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10455 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10456 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10457 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10458 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10459 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10460 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10461 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10462 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10463 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10464 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10465 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10466 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10467 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10468 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10469 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10470 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10471 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10474 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10475 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10476 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10477 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10478 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10479 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10480 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10481 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10482 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10483 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10484 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10485 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10930 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10931 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10932 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10933 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10934 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10935 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10936 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10964 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10965 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10966 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10967 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10968 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10969 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10970 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10971 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10972 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10973 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10974 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10975 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10976 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U10977 + NAND2_X0P5B_A12TUL_C35 + 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0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11320 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11321 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11322 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11323 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11325 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11347 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11348 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11349 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11350 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11351 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11353 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11367 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11370 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11371 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11372 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11373 + INV_X0P6B_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11381 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11383 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11384 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11385 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11386 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11387 + 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+ 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11542 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11543 + NAND2_X0P5B_A12TUL_C35 + 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+ AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11558 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11559 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11560 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11561 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11562 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11563 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11607 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11610 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11611 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11612 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11613 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11614 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11615 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11616 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11617 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11618 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12034 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12035 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12036 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12037 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12038 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12039 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12040 + NAND2_X0P5B_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12048 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12049 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12050 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12051 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12052 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12053 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12054 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12219 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12220 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12221 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12223 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12224 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12225 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12226 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12227 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12229 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12230 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12232 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12249 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12250 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12251 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12252 + NAND2_X0P5B_A12TUL_C35 + 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+ NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12267 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12268 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12270 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12271 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12272 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12287 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12288 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12289 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12290 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12292 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12293 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12349 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12350 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12351 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12353 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12357 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12358 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12359 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12360 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12362 + INV_X0P7M_A12TUL_C35 + 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+ 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12630 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12631 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12633 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12634 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12638 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12639 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12640 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12641 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12642 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12643 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12645 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12647 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12648 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12649 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12650 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12651 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12652 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12653 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12654 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12655 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12656 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12657 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12658 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12659 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12660 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12661 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12662 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12663 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12664 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12665 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12666 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12667 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12668 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12669 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12670 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12671 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12672 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12673 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12674 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12675 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12676 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12677 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12678 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12679 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12680 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12681 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12682 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12683 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12684 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12685 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12686 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12687 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12688 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12689 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12690 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12691 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12692 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12693 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12694 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12695 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12696 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12697 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12698 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12699 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12700 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12701 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12702 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12703 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12704 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12705 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12706 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12707 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12708 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12709 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12710 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12711 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12719 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12720 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12721 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12722 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12723 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12724 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12725 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12760 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12761 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12762 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12763 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12764 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12765 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12766 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12767 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12769 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12770 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12771 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12772 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12773 + OAI21_X1P4M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12781 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12782 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12783 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12784 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12785 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12786 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12787 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12788 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12789 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12790 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12791 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12792 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12793 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12794 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12795 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12796 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12797 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12798 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12799 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12800 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12801 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12802 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12803 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12804 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12805 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12806 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12807 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12808 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12809 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12810 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12811 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12812 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12813 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12814 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12815 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12816 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12817 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12818 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12819 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12820 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12821 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12822 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12823 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12824 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12825 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12826 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12827 + NOR2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12828 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12829 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12830 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12831 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12832 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12833 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12834 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12835 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12836 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12837 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12838 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12839 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12840 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12841 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12842 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12843 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12844 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12845 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12846 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12847 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12848 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12849 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12850 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12851 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12852 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12853 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12854 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12855 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12856 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13041 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13042 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13043 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13044 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13045 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13046 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13047 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13774 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13775 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13776 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13777 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13778 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13779 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13780 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13781 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13782 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13783 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13784 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13785 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13786 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13787 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13788 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13789 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13790 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13791 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13792 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13793 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13794 + 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NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13802 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13803 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13804 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13805 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13806 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13807 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13815 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13816 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13817 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13818 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13819 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13820 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13821 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13822 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13823 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13824 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13825 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13826 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13827 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13828 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13829 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13830 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13831 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13832 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13833 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13834 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13835 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13836 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13837 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13838 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13839 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13840 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13841 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13842 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13843 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13844 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13845 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13846 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13847 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13848 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13849 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13857 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13858 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13859 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13860 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13861 + AO21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13862 + AO21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13863 + 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14036 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14037 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14038 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14039 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14040 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14041 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14042 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14050 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14051 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14052 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14053 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14054 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14055 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14056 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14057 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14058 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14059 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14060 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14061 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14062 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14063 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14064 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14065 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14066 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14067 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14068 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14069 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14070 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14071 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14072 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14073 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14074 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14075 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14076 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14077 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14078 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14079 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14080 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14081 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14082 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14083 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14084 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14085 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14086 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14087 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14088 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14089 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14090 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14091 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14092 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14093 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14094 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14095 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14096 + OAI21B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14097 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14098 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14099 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14100 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14101 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14102 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14103 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14104 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14106 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14107 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14108 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14109 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14110 + AO21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14112 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14114 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14115 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14116 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14117 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14118 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14119 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14120 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14121 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14122 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14123 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14124 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14125 + OAI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14126 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14127 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14128 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14129 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14130 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14131 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14132 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14133 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14134 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14135 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14136 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14137 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14138 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14139 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14140 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14141 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14142 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14143 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14144 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14145 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14146 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14147 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14148 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14149 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14150 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14151 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14152 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14153 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14154 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14155 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14156 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14157 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14158 + AO21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14159 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14160 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14161 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14162 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14163 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14164 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14165 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14166 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14167 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14168 + OAI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14169 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14170 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14171 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14172 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14173 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14174 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14175 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14176 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14177 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14178 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14179 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14181 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14182 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+ NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14903 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14904 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14905 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14906 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14907 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14908 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14909 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14910 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14911 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14912 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14913 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14914 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14915 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16286 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16287 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16288 + AO21A1AI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16289 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16290 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16291 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16292 + MXT2_X1P4M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17071 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17072 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17073 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17074 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17075 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17076 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17077 + 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+ OAI22BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17119 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17120 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17121 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17122 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17123 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17124 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17207 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17208 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17209 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17210 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17211 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17212 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17213 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17214 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17215 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17216 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17217 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17218 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17219 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17220 + 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+ AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17228 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17229 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17230 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17232 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17233 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17241 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17242 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17243 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17244 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17245 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17246 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17247 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17248 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17249 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17250 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17251 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17252 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17253 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17254 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17255 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17256 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17257 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17258 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17259 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17260 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17261 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17262 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17263 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17264 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17265 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17266 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17267 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17618 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17619 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17620 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17621 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17622 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17623 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17624 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17625 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17626 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17627 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17628 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17629 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17630 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17631 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17632 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17633 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17634 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17635 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17636 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17637 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17638 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17639 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17640 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17641 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17642 + OA21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17643 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17644 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17645 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17646 + OA21A1OI2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17647 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17648 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17649 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17650 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17651 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17652 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17653 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17654 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17655 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17656 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17657 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17658 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17659 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17660 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17661 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17662 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17663 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17664 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17665 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17666 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17667 + OA21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17668 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17669 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17670 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17671 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17672 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17673 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17674 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17675 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17676 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17677 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17678 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17679 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17680 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17681 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17682 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17683 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17684 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17685 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18029 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18030 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18031 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18032 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18033 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18034 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18035 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18036 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18037 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18038 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18039 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18040 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18041 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18042 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18057 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18058 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18059 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18060 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18061 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18062 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18063 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18064 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18065 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18066 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18067 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18068 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18069 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18070 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18071 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18072 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18073 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18074 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18075 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18076 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18077 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18078 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18079 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18080 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18081 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18082 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18083 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18084 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18085 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18086 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18087 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18088 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18089 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18090 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18091 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18092 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18093 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18094 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18095 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18096 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18097 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18098 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18406 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18407 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18408 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18409 + XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18410 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18411 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U18412 + XNOR2_X0P7M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19350 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19351 + MXT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19352 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19355 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19357 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19360 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19361 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19362 + AO21A1AI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19363 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19364 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19365 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19366 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19367 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19368 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19369 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19370 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19371 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19372 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19373 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19374 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19375 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19376 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19377 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19378 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19379 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19380 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19381 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19382 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19383 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19384 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19385 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19386 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19387 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19388 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19389 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19390 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19391 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19392 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19393 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19394 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19395 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19396 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19397 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19398 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19399 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19400 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19401 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19402 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19403 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19404 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19405 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19406 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19407 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19408 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19409 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19410 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19411 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19412 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19413 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19414 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19415 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19416 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19417 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19418 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19419 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19420 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19421 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19422 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19423 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19424 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19425 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19426 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19427 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19428 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19429 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19430 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19431 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19432 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19433 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19434 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19435 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19436 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19437 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19438 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19439 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19440 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19441 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19442 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19443 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19444 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19445 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19446 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19447 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19448 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19449 + AO21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19450 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19451 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19452 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19453 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19454 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19455 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19456 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19457 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19458 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19459 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19460 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19461 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19462 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19463 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19464 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19465 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19466 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19467 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19468 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19469 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19470 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19471 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19473 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19474 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19475 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19476 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19477 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19478 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19479 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19480 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19481 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19484 + NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19485 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19486 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19487 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19488 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19489 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19490 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19491 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19494 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19495 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19496 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19497 + CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19498 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19499 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19500 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19501 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19502 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19503 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19504 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19505 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19506 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19507 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19508 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19509 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19510 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19511 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19512 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U19513 + NOR2_X2A_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24354 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24355 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24356 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24357 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24358 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24359 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24360 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24361 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24362 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24363 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24364 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24365 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24373 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24374 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24375 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24376 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24377 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24378 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U24379 + ADDF_X1M_A12TUL_C35 + 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26843 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26844 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26845 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26846 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26847 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26848 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26849 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26850 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26851 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26852 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26853 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26854 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26855 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26856 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26857 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26858 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U26859 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_44J8_122_6278_U33 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U266 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U267 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U268 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U269 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U270 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U271 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U272 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U273 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U274 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U275 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U276 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U277 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U278 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U279 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U280 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U281 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U282 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U283 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U284 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U285 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U286 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U287 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U288 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U289 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U290 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U291 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U292 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U293 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U294 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U295 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U296 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U297 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U298 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U299 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U300 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U301 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U302 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U303 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U304 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U305 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U306 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U307 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U308 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U309 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U310 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U311 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U312 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U313 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U314 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U315 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U316 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U317 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U318 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U319 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U320 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U321 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U322 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U323 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U324 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U325 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U326 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U327 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U328 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 mo +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U355 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U356 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U357 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U358 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U359 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U360 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U361 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U362 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U364 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U365 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U366 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U367 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U369 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U370 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U371 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U372 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U373 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U374 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U375 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U376 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U377 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U378 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U380 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U381 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U382 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U383 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U384 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U386 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U387 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U388 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U389 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U390 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U391 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U392 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U393 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U394 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U395 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U396 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U397 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U399 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U400 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U401 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U402 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U403 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U404 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U406 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U407 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U408 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U409 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U410 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U411 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U412 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U413 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U414 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U415 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U416 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U417 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U418 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U419 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U421 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U422 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U423 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U424 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U425 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U426 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U427 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U429 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U430 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U431 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U432 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U433 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U434 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U435 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U436 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U437 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U438 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U439 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U440 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U441 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U442 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U443 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U444 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U446 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U447 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U448 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U449 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U450 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U451 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U452 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U453 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U455 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U456 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U457 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U458 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U459 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U460 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U461 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U462 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U463 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U464 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U465 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U466 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U467 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U468 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U469 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U470 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U471 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U472 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U474 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U475 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U476 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U477 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U478 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U479 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U480 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U481 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U482 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U484 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U485 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U486 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U487 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U488 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U489 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U490 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U491 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U492 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U494 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U495 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U496 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U497 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U498 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U499 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U500 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U501 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U502 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U503 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U504 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U505 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U506 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U507 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U508 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U509 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U510 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U511 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U512 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U513 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U514 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U515 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U516 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U517 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U518 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U519 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U520 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U521 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U522 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U523 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U524 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U525 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U526 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U527 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U528 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U529 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U530 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U531 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U532 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U533 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U534 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U535 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U536 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U537 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U538 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U539 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U540 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U541 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U542 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U543 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U544 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U545 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U546 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U547 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U548 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U549 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U550 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U551 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U552 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U553 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U554 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U555 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U556 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U557 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U558 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U559 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U560 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U561 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U562 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U563 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U564 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U565 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U566 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U567 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U568 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U569 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U570 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U571 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U572 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U573 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U574 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U575 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U576 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U577 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U578 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U579 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U580 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U581 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U582 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U583 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U584 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U585 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U586 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U587 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U588 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U589 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U590 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U591 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U592 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U593 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U594 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U595 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U596 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U597 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U598 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U599 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U600 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U601 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U602 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U603 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U604 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U605 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U606 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U607 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U608 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U609 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U610 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U611 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U612 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U613 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U614 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U615 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U616 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U617 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U618 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U619 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U620 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U621 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U622 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U623 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U624 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U625 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U626 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U627 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U628 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U629 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U630 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U631 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U632 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U633 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U634 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U635 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U636 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U637 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U638 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U639 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U640 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U641 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U642 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U643 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U644 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U645 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U646 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U647 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U648 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U649 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U650 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U651 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U652 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U653 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U654 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U655 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U656 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U657 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U658 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U659 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U660 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U661 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U662 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U663 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U664 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2323 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2324 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2325 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2326 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2327 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2328 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2329 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2330 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2331 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2332 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2333 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2334 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2335 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2336 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2337 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2338 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2340 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2343 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2345 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2346 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2347 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2348 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2349 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2350 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2351 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2352 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2353 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_DP_OP_47J8_126_5279_U2354 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 mo, r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U3 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U15 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U16 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U20 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U22 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U25 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U27 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U29 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U30 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U40 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U41 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U42 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U43 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U44 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U45 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U46 + OA22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U47 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U48 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U49 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U50 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U51 + OR2_X2M_A12TUL_C35 + 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1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2130 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2131 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2132 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2133 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2134 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2135 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2136 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2137 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2138 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2139 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2140 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2141 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2142 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2143 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2207 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2208 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2209 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2210 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2211 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2212 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2213 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 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1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2256 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2257 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2258 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2259 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2260 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2261 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2262 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2291 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2292 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2293 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2294 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2295 + INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2296 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2297 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2529 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2530 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2531 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2533 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2534 + AO21A1AI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U2535 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4934 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4935 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4936 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4937 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4938 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4939 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U4940 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5422 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5423 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5424 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5425 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5426 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5427 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U5428 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13913 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13914 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13915 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13916 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13917 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13918 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13919 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13920 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13921 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13922 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13923 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13924 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13925 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13926 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13927 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13928 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13929 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13930 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13931 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13932 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13933 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13934 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13935 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13936 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13937 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13938 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13939 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13940 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13941 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13942 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13943 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13944 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13945 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13946 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13947 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13948 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13949 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13950 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13951 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13952 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13953 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13954 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13955 + CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13956 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13957 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13958 + CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13959 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13960 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13961 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13962 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13963 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13964 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13965 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13966 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13967 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13968 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13969 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13970 + OA21A1OI2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13971 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13972 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13973 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13974 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13975 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13976 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13977 + CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13978 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13979 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13980 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13981 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+ MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18960 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18961 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18962 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18963 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18964 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18965 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18966 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18967 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18968 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18969 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18970 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18971 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18972 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18987 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18988 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18989 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18990 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18991 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18992 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U18993 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19008 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19009 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19010 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19011 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19012 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19013 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19014 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19015 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19016 + OAI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19017 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19018 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19019 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19020 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19021 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19022 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19023 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19024 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19025 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19026 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19027 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19028 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19029 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19030 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19031 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19032 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19033 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19034 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19035 + 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1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19098 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19099 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19100 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19101 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19102 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19103 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19104 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19105 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19106 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19107 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19108 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19109 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19110 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19111 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19112 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19113 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19114 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19115 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19116 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19117 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19118 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19119 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19120 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19121 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19123 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U19125 + NOR2_X1A_A12TUL_C35 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21668 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21669 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21670 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21671 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21672 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21673 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21674 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21675 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21676 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21677 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21678 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21679 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21680 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U21681 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24172 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24173 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24174 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24175 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24176 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24177 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24178 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24179 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24180 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24181 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24182 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24183 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24184 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24186 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24187 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24188 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24189 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24190 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24191 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24192 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24255 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24256 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24257 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24258 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24259 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24260 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24261 + 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+ MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24276 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24277 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24278 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24279 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24280 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U24281 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26885 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26886 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26887 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26888 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26889 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26890 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26891 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26892 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26893 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26894 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26895 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26896 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26897 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26898 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26899 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26900 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26901 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26903 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26904 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26905 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U26906 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U6 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U10 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U11 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U13 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U15 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U16 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U19 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U22 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U23 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U24 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U25 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U27 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U28 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U30 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U31 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U32 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U33 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U34 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U35 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U36 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U37 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U38 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U39 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U40 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U41 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U43 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U44 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U45 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U46 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U47 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U48 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U49 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U51 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U52 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U53 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U54 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U55 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U56 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U57 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U58 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U59 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U60 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U61 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U62 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U63 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U64 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U66 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U67 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U68 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U69 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U70 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U71 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U72 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U73 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U74 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U75 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U76 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U77 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U78 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U79 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U80 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U81 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U82 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U83 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U84 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U85 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U86 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U87 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U88 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U89 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U90 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U91 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U92 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U93 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U94 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U95 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U96 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U97 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U98 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U99 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U100 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U101 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U102 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U103 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U104 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U105 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U106 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U107 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U108 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U110 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U111 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U112 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U113 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U114 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U115 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U116 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U117 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U118 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U119 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U120 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U121 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U122 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U123 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U124 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U125 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U126 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U127 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U128 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U129 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U130 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U131 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U132 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U133 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U134 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U135 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U136 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U138 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U139 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U140 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U141 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U142 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U144 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U145 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U146 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U1 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U2 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U4 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpgpu_inst_valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_valids_counter_U2 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_valids_counter_U4 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_U2 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_U3 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_U4 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_U5 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U1 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U2 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U3 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U5 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U6 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U12 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U13 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U14 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U15 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U16 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U17 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U18 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U19 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U20 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U3 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U4 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U5 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U6 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U7 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U8 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U9 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U10 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U11 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U12 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U13 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U14 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U15 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U16 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U17 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U18 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U19 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U20 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U21 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U22 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U23 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U24 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U25 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U26 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U27 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U28 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U29 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U30 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U31 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U32 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U33 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U34 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U35 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U36 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U37 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U38 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U39 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U40 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U41 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U42 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U43 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U44 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U45 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U46 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U47 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U48 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U49 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U50 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U51 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U52 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U53 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U54 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U55 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U56 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U57 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U58 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U59 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U60 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U61 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U62 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_value_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_32_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_33_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_34_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_35_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_36_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_37_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_38_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_39_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_40_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_41_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_42_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_43_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_44_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_45_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_46_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_47_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_48_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_49_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_50_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_51_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_52_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_53_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_54_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_55_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_56_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_57_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_58_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_59_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U4 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U7 + BUF_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U8 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U9 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U10 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U11 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U12 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U13 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U14 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U15 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U16 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U17 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U18 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U19 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U20 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U21 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U22 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U23 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U24 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U25 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U26 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U27 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U28 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U29 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U30 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U31 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U32 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U33 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U34 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U35 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U36 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U37 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U38 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U39 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U40 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U41 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U42 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U43 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U44 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U45 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U46 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U47 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U48 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U49 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U50 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U51 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U52 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U53 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U54 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U55 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U56 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U57 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U58 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U59 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U60 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U61 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U62 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U63 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U64 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U65 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U66 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U67 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U68 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U69 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U70 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U71 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U72 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U73 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U74 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U75 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U76 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U77 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U78 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U79 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U80 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U81 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U82 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U83 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U84 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U85 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U86 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U87 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U88 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U89 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U90 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U91 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U92 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U93 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U94 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U95 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U96 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U97 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U98 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U99 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U100 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U101 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U102 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U103 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U104 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U105 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U106 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U107 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U108 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U109 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U110 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U111 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U112 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U113 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U114 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U115 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U116 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U117 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U118 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U119 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U120 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U121 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U122 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U123 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U124 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U125 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U126 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U127 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U128 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U129 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U130 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U131 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U132 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U133 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U134 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U135 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U136 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U137 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U138 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U139 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U140 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U141 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U142 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U143 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U144 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U145 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U146 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U147 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U148 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U149 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U150 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U151 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U152 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U153 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U154 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U155 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U156 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U157 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U158 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U159 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U160 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U161 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U162 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U163 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U164 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U165 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U166 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U167 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U168 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U169 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U170 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U171 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U172 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U173 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U174 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U175 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U176 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U177 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U178 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U179 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U180 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U181 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U182 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U183 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U184 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U185 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U186 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U187 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U188 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U189 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U190 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U191 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U192 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U193 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U194 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U195 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U196 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U197 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U198 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U199 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U200 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U201 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U202 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U203 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U204 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U205 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U206 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U207 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U208 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U209 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U210 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U211 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U212 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U213 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U214 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U215 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U216 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U217 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U218 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U219 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U220 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U221 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U222 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U223 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U224 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U225 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U226 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U227 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U228 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U229 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U230 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U231 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U232 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U233 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U234 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U235 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U236 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U237 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U238 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U239 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U240 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U241 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U242 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U243 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U244 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U245 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U246 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U247 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U248 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U249 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U250 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U251 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U252 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U253 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U254 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U255 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U256 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U257 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U258 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U259 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U260 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U261 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U262 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U263 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U264 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U265 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U266 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U267 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U268 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U269 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U270 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U271 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U272 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U273 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U274 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U275 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U276 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U277 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U278 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U279 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U280 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U281 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U282 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U283 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U284 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U285 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U286 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U287 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U288 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U289 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U290 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U291 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U292 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U293 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U294 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U295 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U296 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U297 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U298 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U299 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U300 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U301 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U302 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U303 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U304 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U305 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U306 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U307 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U308 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U309 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U310 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U311 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U312 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U313 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U314 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U315 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U316 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U317 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U318 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U319 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U320 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U321 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U322 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U323 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U324 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U325 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U326 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U327 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U328 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U329 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U330 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U331 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U332 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U333 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U334 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U335 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U336 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U337 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U338 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U339 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U340 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U341 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U342 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U343 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U344 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U345 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U346 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U347 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U348 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U349 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U350 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U351 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U352 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U353 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U354 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U355 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U356 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U357 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U358 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U359 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U360 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U361 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U362 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U363 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U364 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U365 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U366 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U367 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U368 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U369 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U370 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U371 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U372 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U373 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U374 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U375 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U376 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U377 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U378 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U379 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U380 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U381 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U382 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U383 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U384 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U385 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U386 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U387 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U388 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U389 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U390 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U391 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U392 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U393 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U394 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U395 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U396 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U397 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U398 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U399 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U400 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U401 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U402 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U403 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U404 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U405 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U406 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U407 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U408 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U409 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U410 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U411 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U412 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U413 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U414 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U415 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U416 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U417 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U418 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U419 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U420 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U421 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U422 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U423 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U424 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U425 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U426 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U427 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U428 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U429 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U430 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U431 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U432 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U433 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U434 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U435 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U436 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U437 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U438 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U439 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U440 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U441 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U442 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U443 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U444 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U445 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U446 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U447 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U448 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U449 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U450 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U451 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U452 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U453 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U454 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U455 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U456 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U457 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U458 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U459 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U460 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_32_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_33_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_34_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_35_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_36_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_37_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_38_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_39_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_40_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_41_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_42_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_43_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_44_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_45_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_46_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_47_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_48_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_49_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_50_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_51_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_52_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_53_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_54_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_55_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_56_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_57_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_58_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_59_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_60_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_61_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_62_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_63_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_64_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_65_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_66_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_67_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_68_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_69_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_70_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_71_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_72_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_73_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_74_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_75_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_76_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_77_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_78_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_79_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_80_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_81_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_82_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_83_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_84_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_85_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_86_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_87_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_88_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_89_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_90_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_91_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_92_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_93_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_94_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_95_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_96_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_97_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_98_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_99_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_100_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_101_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_102_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_103_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_104_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_105_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_106_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_107_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_108_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_109_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_110_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_111_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_112_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_113_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_114_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_115_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_116_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_117_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_118_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_119_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_120_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_121_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_122_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_123_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_124_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_125_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_126_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_127_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_128_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_129_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_130_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_131_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_132_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_133_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_134_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_135_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_136_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_137_ + DFFSQN_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_138_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_139_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_140_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_141_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_142_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_143_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_144_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_145_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_146_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_147_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_148_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_149_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_150_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_151_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_152_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_153_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_154_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_155_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_156_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_157_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_158_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_159_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_160_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_161_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_162_ + DFFSQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_163_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_164_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_165_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_166_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_167_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_168_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_169_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_170_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_171_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_172_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_173_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_174_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_175_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_176_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_177_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_178_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_179_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_180_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_181_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_182_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_183_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_184_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_185_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_186_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_187_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_188_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_189_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_190_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_191_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_192_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_193_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_194_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_195_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_196_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_197_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_198_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_199_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_200_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_201_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_202_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_203_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_204_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_205_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_206_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_207_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_208_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_209_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_210_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_211_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_212_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_213_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_214_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_215_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_216_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_217_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_218_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_219_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_220_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_221_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_222_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_223_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_224_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_225_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_226_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_227_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_228_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_229_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_230_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_231_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_232_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_233_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_234_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_235_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_236_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_237_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_238_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_239_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_240_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_241_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_242_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_243_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_244_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_245_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_246_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_247_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_248_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_249_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_250_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_251_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_252_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_253_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_254_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_255_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_256_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_257_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_258_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_259_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_260_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_261_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_262_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_263_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_264_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_265_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_266_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_267_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_268_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_269_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_270_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_271_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_272_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_273_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_274_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_275_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_276_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_277_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_278_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_279_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_280_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_281_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_282_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_283_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_284_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_285_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_286_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_287_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_288_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_289_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_290_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_291_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_292_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_293_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_294_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_295_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_296_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_297_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_298_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_299_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_300_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_301_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_302_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_303_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_304_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_305_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_306_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_307_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_308_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_309_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_310_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_311_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_312_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_313_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_314_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_315_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_316_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_317_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_318_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_319_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_320_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_321_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_322_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_323_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_324_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_325_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_326_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_327_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_328_ + DFFSQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_329_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_330_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_331_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_332_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_333_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_334_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_335_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_336_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_337_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_338_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_339_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_340_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_341_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_342_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_343_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_344_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_345_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_346_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_347_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_348_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_349_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_350_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_351_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_352_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_353_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_354_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_355_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_356_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_357_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_358_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_359_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_360_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_361_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_362_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_363_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_364_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_365_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_366_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_367_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_368_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_369_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_370_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_371_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_372_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_373_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_374_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_375_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_376_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_377_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_378_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_379_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_380_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_381_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_382_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_383_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_384_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_385_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_386_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_387_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_388_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_389_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_390_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_391_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_392_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_393_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_394_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_395_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_396_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_397_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_398_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_399_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_400_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_401_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_402_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_403_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_404_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_405_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_406_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_407_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_408_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_409_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_410_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_411_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_412_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_413_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_414_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_415_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_416_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_417_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_418_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_419_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_420_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_421_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_422_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_423_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_424_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_425_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_426_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_427_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_428_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_429_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_430_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_431_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_432_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_433_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_434_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_435_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_436_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_437_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_438_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_439_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_440_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_441_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_442_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_443_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_444_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_445_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_446_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_447_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_448_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_449_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_450_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_451_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_452_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_453_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_454_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_455_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_456_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_457_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_458_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_459_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_460_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_461_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_462_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_463_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_464_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_465_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_466_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_467_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_468_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_469_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_470_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_471_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_472_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_473_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_474_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_475_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_476_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_477_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_478_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_479_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_480_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_481_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_482_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_483_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_484_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_485_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_486_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_U3 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U4 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U5 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U6 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U7 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U8 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U9 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U10 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U11 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U12 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U13 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U14 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U15 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U16 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U17 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U18 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U19 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U20 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U21 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U22 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U23 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U24 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U25 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U26 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U27 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U28 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U29 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U30 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U31 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U32 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U33 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U34 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U35 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U36 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U37 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U38 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U39 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U40 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U41 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U42 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U43 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U44 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U45 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U46 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U47 + NOR2XB_X0P5M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U55 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U56 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U57 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U58 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U59 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U60 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U61 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U62 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U63 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U64 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U65 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U66 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U67 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U68 + NOR2B_X0P5M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U76 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U77 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U78 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U79 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U80 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U81 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U82 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U83 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U84 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U85 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U86 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U87 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U88 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U89 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U90 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U91 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U92 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U93 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U94 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U95 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U96 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U97 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U98 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U99 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U100 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U101 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U102 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U103 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U104 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U105 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U106 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U107 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U108 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U109 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U110 + NOR2B_X0P5M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U118 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U119 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U120 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U121 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U122 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U123 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U124 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U125 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U126 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U127 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U128 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U129 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U130 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U131 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U132 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U133 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U134 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U135 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U136 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U137 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U138 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U139 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U140 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U141 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U142 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U143 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U144 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U145 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U146 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U147 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U148 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U149 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U150 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U151 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U152 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U153 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U154 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U155 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U156 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U157 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U158 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U159 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U160 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U161 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U162 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U163 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U164 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U165 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U166 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U167 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U168 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U169 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U170 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U171 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U172 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U173 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U174 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U175 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U176 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U177 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U178 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U179 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U180 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U181 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U182 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U183 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U184 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U185 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U186 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U187 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U188 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U189 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U190 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U191 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U192 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U193 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U194 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U195 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U196 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U197 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U198 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U199 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U200 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U201 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U202 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U203 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U204 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U205 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U206 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U207 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_32_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_33_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_34_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_35_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_36_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_37_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_38_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_39_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_40_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_41_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_42_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_43_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_44_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_45_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_46_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_47_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_48_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_49_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_50_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_51_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_52_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_53_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_54_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_55_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_56_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_57_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_58_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_59_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_60_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_61_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_62_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_63_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_64_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_65_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_66_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_67_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_68_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_69_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_70_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_71_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_72_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_73_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_74_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_75_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_76_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_77_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_78_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_79_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_80_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_81_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_82_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_83_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_84_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_85_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_86_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_87_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_88_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_89_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_90_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_91_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_92_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_93_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_94_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_95_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_96_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_97_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_98_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_99_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_100_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_101_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_102_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_103_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_104_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_105_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_106_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_107_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_108_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_109_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_110_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_111_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_112_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_113_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_114_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_115_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_116_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_117_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_118_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_119_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_120_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_121_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_122_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_123_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_124_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_125_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_126_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_127_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_128_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_129_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_130_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_131_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_132_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_133_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_134_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_135_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_136_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_137_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_138_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_139_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_140_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_141_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_142_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_143_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_144_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_145_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_146_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_147_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_148_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_149_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_150_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_151_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_152_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_153_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_154_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_155_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_156_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_157_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_158_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_159_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_160_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_161_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_162_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_163_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_164_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_165_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_166_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_167_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_168_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_169_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_170_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_171_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_172_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_173_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_174_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_175_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_176_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_177_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_178_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_179_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_180_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_181_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_182_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_183_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_184_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_185_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_186_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_187_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_188_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_189_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_190_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_191_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_192_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_193_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_194_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_195_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_196_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_197_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_198_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_199_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_200_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_201_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_202_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_U3 + BUF_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_lsu_reg_U4 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_lsu_reg_U5 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U6 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U7 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U8 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U9 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U10 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U11 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U12 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U13 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U14 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U15 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U16 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U17 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U18 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U19 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U20 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U21 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U22 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U23 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U24 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U25 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U26 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U27 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U28 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U29 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U30 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U31 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U32 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U33 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U34 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U35 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U36 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U37 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U38 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U39 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U40 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U41 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U42 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U43 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U44 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U45 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U46 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U47 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U48 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U49 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U50 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U51 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U52 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U53 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U54 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U55 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U56 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U57 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U58 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U59 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U60 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U61 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U62 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U63 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U64 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U76 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_lsu_reg_U77 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U78 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U79 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U80 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U81 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U82 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U83 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U84 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U85 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U86 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U87 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U88 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U89 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U90 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U91 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U92 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U93 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U94 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U95 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U96 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U97 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U98 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U99 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U100 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_lsu_reg_U101 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_lsu_reg_U102 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U103 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U104 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U105 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U149 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U150 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U151 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U152 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U153 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U154 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U155 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U157 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U158 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U159 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U160 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U161 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U162 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U163 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U164 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U165 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U166 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U167 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U168 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U169 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U170 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U171 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U172 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U173 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U174 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U175 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U176 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U177 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U178 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U179 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U180 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U181 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U182 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U183 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U184 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U185 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U186 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U187 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U188 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U189 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U190 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U191 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U192 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U193 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U194 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U195 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U196 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U197 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U198 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U199 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U200 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U201 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U202 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U203 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U204 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U205 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U206 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U207 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U208 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U209 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U210 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U211 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U212 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U213 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U214 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U215 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U216 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U217 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U218 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U219 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U220 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U221 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U222 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U223 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U224 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U225 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U226 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U227 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U228 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U229 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U230 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U231 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U232 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U233 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U234 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U235 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U236 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U237 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U238 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U239 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U240 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U241 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U242 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U243 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U244 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U245 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U246 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U247 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U248 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U249 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U250 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U251 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U252 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U253 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U254 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U255 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U256 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U257 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U258 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U259 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U260 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U261 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U262 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U263 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U264 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U265 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U266 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U267 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U268 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U269 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U270 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U271 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U272 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U273 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U274 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U275 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U276 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U277 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U278 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U279 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U280 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U281 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U282 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U283 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U284 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U285 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U286 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U287 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U288 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U289 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U290 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U291 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U292 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U293 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U294 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U295 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U296 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U297 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U298 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U299 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U300 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U301 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U302 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U303 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U304 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U305 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U306 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U307 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U308 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U309 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U310 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U311 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U312 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U313 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U314 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U315 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U316 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_32_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_33_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_34_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_35_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_36_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_37_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_38_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_39_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_40_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_41_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_42_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_43_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_44_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_45_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_46_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_47_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_48_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_49_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_50_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_51_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_52_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_53_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_54_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_55_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_56_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_57_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_58_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_59_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_60_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_61_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_62_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_63_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_64_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_65_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_66_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_67_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_68_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_69_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_70_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_71_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_72_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_73_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_74_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_75_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_76_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_77_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_78_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_79_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_80_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_81_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_82_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_83_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_84_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_85_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_86_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_87_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_88_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_89_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_90_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_91_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_92_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_93_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_94_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_95_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_96_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_97_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_98_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_99_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_100_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_101_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_102_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_103_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_104_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_105_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_106_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_107_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_108_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_109_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_110_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_111_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_112_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_113_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_114_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_115_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_116_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_117_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_118_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_119_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_120_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_121_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_122_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_123_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_124_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_125_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_126_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_127_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_128_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_129_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_130_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_131_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_132_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_133_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_134_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_135_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_136_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_137_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_138_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_139_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_140_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_141_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_142_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_143_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_144_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_145_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_146_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_147_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_148_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_149_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_150_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_151_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_152_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_153_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_154_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_155_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_156_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_157_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_158_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_159_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_160_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_161_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_162_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_163_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_164_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_165_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_166_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_167_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_168_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_169_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_170_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_171_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_172_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_173_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_174_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_175_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_176_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_177_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_178_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_179_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_180_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_181_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_182_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_183_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_184_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_185_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_186_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_187_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_188_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_189_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_190_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_191_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_192_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_193_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_194_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_195_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_196_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_197_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_198_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_199_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_200_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_201_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_202_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_203_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_204_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_205_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_206_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_207_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_208_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_209_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_210_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_211_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_212_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_213_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_214_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_215_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_216_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_217_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_218_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_219_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_220_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_221_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_222_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_223_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_224_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_225_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_226_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_227_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_228_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_229_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_230_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_231_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_232_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_233_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_234_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_235_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_236_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_237_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_238_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_239_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_240_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_241_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_242_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_243_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_244_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_245_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_246_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_247_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_248_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_249_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_250_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_251_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_252_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_253_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_254_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_255_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_256_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_257_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_258_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_259_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_260_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_261_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_262_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_263_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_264_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_265_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_266_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_267_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_268_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_269_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_270_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_271_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_272_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_273_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_274_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_275_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_276_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_277_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_278_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_279_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_280_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_281_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_282_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_283_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_284_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_285_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_286_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_287_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_288_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_289_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_290_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_291_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_292_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_293_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_294_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_295_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_296_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_297_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_298_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_299_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_300_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_301_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_302_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_303_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_304_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_305_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_306_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_307_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U2 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U3 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U4 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U5 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U6 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U8 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U9 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U10 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U11 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U12 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U13 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U14 + BUF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U15 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U16 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U18 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U19 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U20 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U21 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U22 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U23 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U24 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U26 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U27 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U28 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U29 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U30 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U31 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U32 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U33 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U39 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U40 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U41 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U46 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U47 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U48 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U49 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U50 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U51 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U52 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U53 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U54 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U55 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U56 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U57 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U58 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U59 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U60 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U61 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U62 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U63 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U64 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U65 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U66 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U67 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U68 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U69 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U70 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U71 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U72 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U73 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U74 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U75 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U76 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U77 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U78 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U79 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U80 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U81 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U82 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U83 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U84 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U85 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U86 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U87 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U88 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U89 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U90 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U91 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U92 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U93 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U94 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U95 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U96 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U97 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U98 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U99 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U101 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U102 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U104 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U107 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U108 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U113 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U118 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U119 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U124 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U130 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U136 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U142 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U148 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U154 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U160 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U166 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U172 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U178 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U184 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U190 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U196 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U201 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U207 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U213 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U214 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U219 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U220 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U221 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U225 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U230 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U235 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U241 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U246 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U247 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U248 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U251 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U252 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U254 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U257 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U263 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U269 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U273 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U274 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U279 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U282 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U283 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U285 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U291 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U296 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U297 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U299 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U302 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U307 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U309 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U310 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U312 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U313 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U315 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U316 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U317 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U318 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U319 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U322 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U323 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U324 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U326 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U327 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U328 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U330 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U332 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U333 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U334 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U336 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U339 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U341 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U342 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U344 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U345 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U346 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U347 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U351 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U352 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U353 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U354 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U355 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U357 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U358 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U360 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U361 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U362 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U363 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U364 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U366 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U368 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U370 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U372 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U373 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U374 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U376 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U379 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U380 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U382 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U387 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U388 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U389 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U390 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U392 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U393 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U394 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U396 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U398 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U399 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U400 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U401 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U402 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U403 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U404 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U405 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U407 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U409 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U411 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U412 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U416 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U419 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U421 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U426 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U430 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U431 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U432 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U433 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U434 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U435 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U437 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U438 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U439 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U440 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U443 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U444 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U445 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U449 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U450 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U455 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U456 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U457 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U460 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U461 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U462 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U463 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U466 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U467 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U468 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U469 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U471 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U472 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U473 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U474 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U475 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U476 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U477 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U478 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U479 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U480 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U481 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U482 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U483 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U484 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U485 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U486 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U487 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U488 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U489 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U490 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U491 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U492 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U493 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U494 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U495 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U496 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U497 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U498 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U499 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U500 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U501 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U502 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U503 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U504 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U505 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U506 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U507 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U508 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U509 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U511 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U512 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U513 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U514 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U515 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U516 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U517 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U518 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U519 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U520 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U521 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U522 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U523 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U524 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U525 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U526 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U527 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U528 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U529 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U530 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U531 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U532 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U533 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U534 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U535 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U536 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U537 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U538 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U539 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U540 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U541 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U542 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U543 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U544 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U545 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U546 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U547 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U548 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U549 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U550 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U551 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U552 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U553 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U554 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U555 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U556 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U557 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U558 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U559 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U560 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U561 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U562 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U563 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U564 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U565 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U566 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U567 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U568 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U569 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U570 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U571 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U572 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U573 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U574 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U575 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U576 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U577 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U578 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U579 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U580 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U581 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U582 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U583 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U585 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U586 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U587 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U588 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U590 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U591 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U592 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U593 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U594 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U595 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U596 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U598 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U599 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U600 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U601 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U602 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U603 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U604 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U605 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U606 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U607 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U608 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U610 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U611 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U612 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U613 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U614 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U615 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U616 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U617 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U618 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U619 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U620 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U621 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U622 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U623 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U624 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U625 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U626 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U627 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U628 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U629 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U630 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U631 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U632 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U634 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U635 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U636 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U637 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U638 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U639 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U640 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U641 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U642 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U643 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U644 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U645 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U646 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U647 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U648 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U649 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U650 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U651 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U652 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U653 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U654 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U655 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U656 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U657 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U658 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U659 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U660 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U661 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U662 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U663 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U664 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U665 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U666 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U667 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U668 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U671 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U672 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U674 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U677 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U678 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U679 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U680 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U683 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U684 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U685 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U686 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U687 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U689 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U690 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U691 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U692 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U693 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U695 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U696 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U697 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U698 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U699 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U700 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U703 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U704 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U705 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U706 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U707 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U708 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U710 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U711 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U712 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U713 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U715 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U716 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U717 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U718 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U719 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U721 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U722 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U724 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U725 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U726 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U728 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U729 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U730 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U731 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U733 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U734 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U736 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U737 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U738 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U739 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U740 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U742 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U743 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U744 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U745 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U747 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U748 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U750 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U751 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U752 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U754 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U755 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U758 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U759 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U760 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U761 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U762 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U763 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U764 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U765 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U766 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U767 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U769 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U770 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U771 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U772 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U773 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U774 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U775 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U777 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U778 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U779 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U780 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U782 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U783 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U784 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U785 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U786 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U788 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U789 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U791 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U792 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U793 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U794 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U796 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U797 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U798 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U800 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U801 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U802 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U803 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U804 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U805 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U806 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U807 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U808 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U809 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U810 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U811 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U812 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U813 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U814 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U815 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U816 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U817 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U818 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U819 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U820 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U823 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U824 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U825 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U827 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U828 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U829 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U830 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U831 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U832 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U833 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U834 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U835 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U836 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U837 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U838 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U839 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U840 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U841 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U842 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U843 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U844 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U845 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U846 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U847 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U848 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U849 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U850 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U851 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U852 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U853 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U856 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U857 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U859 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U861 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U862 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U863 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U864 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U865 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U866 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U867 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U868 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U870 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U871 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U872 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U873 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U874 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U876 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U877 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U878 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U880 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U881 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U882 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U884 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U885 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U887 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U888 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U889 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U890 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U892 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U893 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U894 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U895 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U896 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U897 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U899 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U900 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U902 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U903 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U904 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U905 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U906 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U907 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U908 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U910 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U911 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U912 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U914 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U916 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U918 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U919 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U921 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U922 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U924 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U925 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U926 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U928 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U929 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U931 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U932 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U934 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U935 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U936 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U937 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U938 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U939 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U940 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U941 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U942 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U943 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U944 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U945 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U946 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U947 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U948 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U949 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U950 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U951 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U952 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U953 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U954 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U955 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U957 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U958 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U959 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U960 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U961 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U962 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U963 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U964 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U966 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U967 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U968 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U969 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U970 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U972 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U973 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U975 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U977 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U978 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U980 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U981 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U982 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U983 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U984 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U986 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U987 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U988 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U990 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U991 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U992 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U993 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U994 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U996 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U997 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U998 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U999 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1001 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1004 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1005 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1007 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1008 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1009 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1010 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1011 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1012 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1013 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1014 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1015 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1017 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1018 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1019 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1020 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1021 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1023 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1024 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1025 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1026 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1027 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1028 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1029 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1030 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1031 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1032 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1033 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1034 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1035 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1036 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1037 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1038 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1039 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1040 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1041 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1042 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1043 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1045 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1046 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1047 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1048 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1049 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1050 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1051 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1052 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1053 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1054 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1055 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1056 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1057 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1058 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1061 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1062 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1063 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1064 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1065 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1066 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1067 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1068 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1069 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1070 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1071 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1072 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1073 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1074 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1075 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1076 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1077 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1078 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1080 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1081 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1082 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1083 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1084 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1086 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1087 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1088 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1089 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1090 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1094 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1095 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1097 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1098 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1099 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1103 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1108 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1113 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1117 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1122 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1127 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1132 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1136 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1141 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1146 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1150 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1155 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1160 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1165 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1169 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1174 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1179 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1184 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1188 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1193 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1197 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1202 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1207 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1212 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1216 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1220 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1221 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1226 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1231 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1235 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1240 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1245 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1248 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1250 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1251 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1254 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1257 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1258 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1259 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1264 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1268 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1273 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1275 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1278 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1279 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1280 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1282 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1283 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1286 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1287 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1292 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1296 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1297 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1299 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1302 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1303 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1307 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1308 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1309 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1310 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1312 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1313 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1314 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1315 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1316 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1317 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1318 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1319 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1320 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1322 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1323 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1324 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1325 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1326 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1327 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1328 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1330 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1331 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1332 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1333 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1334 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1336 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1337 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1339 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1341 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1342 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1343 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1344 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1345 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1346 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1347 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1348 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1350 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1351 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1352 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1353 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1354 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1355 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1357 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1359 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1360 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1361 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1362 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1363 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1364 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1365 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1366 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1368 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1370 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1371 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1372 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1373 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1374 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1375 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1376 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1377 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1379 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1380 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1382 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1383 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1385 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1387 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1388 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1389 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1390 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1392 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1393 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1394 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1395 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1396 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1398 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1399 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1400 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1401 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1402 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1403 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1404 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1405 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1406 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1407 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1408 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1409 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1411 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1412 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1417 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1419 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1421 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1425 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1427 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1430 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1431 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1433 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1434 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1435 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1437 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1440 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1443 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1444 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1445 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1449 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1450 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1455 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1457 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1460 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1463 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1465 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1466 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1467 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1468 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1469 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1470 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1471 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1472 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1473 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1474 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1475 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1476 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1477 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1478 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1479 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1480 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1481 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1482 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1483 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1484 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U11 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U11 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U11 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U11 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U7 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U11 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U12 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U13 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U15 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U7 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U11 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U11 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U3 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U4 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U5 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U6 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U8 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U9 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U10 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U11 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U12 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U13 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U15 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U17 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U19 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U21 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_wb_U2 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U3 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U4 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U5 OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U6 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U7 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U8 OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U9 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U10 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U11 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U12 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U13 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U14 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U15 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U16 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U17 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U18 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U19 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U20 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U21 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U22 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U23 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U24 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U25 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U26 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U27 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U28 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U29 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U30 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U31 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U32 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U33 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U34 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U35 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U36 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U37 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U38 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U39 AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U40 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U41 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U42 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U43 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U44 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U45 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U46 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U47 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U48 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U49 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U50 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U51 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U52 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U53 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U54 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U55 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U56 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U57 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U58 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U59 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U60 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U61 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U62 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U63 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U64 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U65 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U66 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U67 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U68 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U69 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U70 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U71 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U72 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U73 NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U74 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U75 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U76 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U77 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U78 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U79 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U80 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U81 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U82 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U83 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U84 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U85 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U86 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U87 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U88 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U89 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U90 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U91 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U92 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U93 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U94 BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U95 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U96 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U97 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U98 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U99 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U100 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U101 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U102 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U103 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U104 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U105 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U106 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U107 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U108 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U109 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U110 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U111 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U112 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U113 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U114 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U115 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U116 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U117 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U118 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U119 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U120 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U121 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U122 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U123 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U124 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U125 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U126 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U127 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U128 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U129 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U130 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U131 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U132 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U133 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U134 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U135 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U136 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U137 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U138 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U139 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U140 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U141 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U142 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U143 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U144 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U145 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U146 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U147 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U148 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U149 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U150 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U151 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U152 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U153 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U154 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U155 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U156 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U157 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U158 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U159 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U160 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U161 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U162 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U163 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U164 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U165 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U166 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U167 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U168 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U169 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U170 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U171 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U172 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U173 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U174 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U175 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U176 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U177 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U178 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U179 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U180 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U181 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U182 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U183 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U184 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U185 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U186 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U187 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U188 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U189 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U190 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U191 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U192 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U193 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U194 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U195 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U196 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U197 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U198 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U199 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U200 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U201 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U202 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U203 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U204 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U205 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U206 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U207 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U208 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U209 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U210 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U211 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U212 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U213 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U214 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U215 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U216 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U217 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U218 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U219 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U220 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U221 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U222 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U223 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U224 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U225 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U226 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U227 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U228 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U229 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U230 BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U231 INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U232 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U233 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U234 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U235 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U236 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U237 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U238 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U239 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U240 AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U241 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U242 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U243 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U244 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U245 NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U246 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U247 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U248 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U249 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U250 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U251 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U252 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U253 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U254 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U255 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U256 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U257 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U258 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U259 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U260 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U261 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U262 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U263 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U264 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U265 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U266 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U267 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U268 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U269 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U270 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U271 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U272 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U273 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U274 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U275 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U276 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U277 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U278 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U279 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U280 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U281 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U282 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U283 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U284 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U285 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U286 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U287 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U288 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U289 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U290 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U291 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U292 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U293 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U294 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U295 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U296 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U297 OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U298 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_wb_U299 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U426 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U427 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U428 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U429 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U430 INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U431 INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U432 INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U433 INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U434 INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U435 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U436 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U437 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U438 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U439 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_load_store_unit_U1 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_load_store_unit_U2 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_load_store_unit_U3 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_load_store_unit_U4 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U1 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U2 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U25 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U32 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U33 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U34 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U35 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U36 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U37 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U38 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U39 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U40 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U41 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U42 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U43 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U44 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U45 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U46 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U47 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U48 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U49 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U50 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U51 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U52 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U53 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U54 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U55 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U56 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U57 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U58 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U59 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U60 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U61 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U62 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U63 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U64 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U65 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U66 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U67 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U68 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U69 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U70 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U71 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U72 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U73 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U74 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U75 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U76 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U77 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U78 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U79 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U80 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U81 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U82 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U83 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U84 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U85 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U86 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U87 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U88 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U89 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U90 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U91 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U92 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U93 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U94 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U95 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U96 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U97 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U98 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U99 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U100 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U101 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U102 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U103 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U104 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U105 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U106 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U107 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U108 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U109 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U110 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U111 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U112 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U113 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U114 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U115 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U116 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U117 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U118 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U119 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U120 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U121 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U122 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U123 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U124 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U125 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U126 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U127 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U128 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_U2 BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_U3 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_U4 BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_U1 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U3 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U4 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U5 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U6 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U7 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U8 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U9 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U12 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U13 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U14 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U15 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U16 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U17 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U18 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U19 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U20 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U21 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U22 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U23 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U28 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U29 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U30 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U31 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U32 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U33 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U34 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U35 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U36 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U37 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U38 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U39 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U40 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U41 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U42 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U43 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U44 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U45 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U46 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U47 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U60 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U61 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U62 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U63 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U64 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U65 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U66 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U67 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U68 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U69 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U70 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U71 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U72 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U73 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U74 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U75 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U76 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U77 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U78 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U79 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U80 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U81 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U82 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U83 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U84 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U85 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U86 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U87 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U88 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U89 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U90 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U91 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U92 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U93 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U94 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U95 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U96 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U97 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U98 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U99 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U100 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U101 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U102 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U103 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U104 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U105 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U106 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U107 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U108 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U109 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U110 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U111 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U112 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U113 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U114 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U115 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U116 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U117 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U118 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U119 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U120 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U121 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U122 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U123 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U124 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U125 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U126 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U127 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U128 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U129 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U130 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U131 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U132 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U133 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U134 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U135 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U136 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U137 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U138 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U139 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U140 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U141 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U142 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U143 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U144 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U145 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U146 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U147 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U148 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U149 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U150 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U151 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U152 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U153 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U154 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U155 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U156 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U157 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U158 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U159 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U160 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U161 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U162 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U163 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U164 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U165 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U166 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U167 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U168 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U169 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U170 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U171 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U172 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U173 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U174 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U175 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U176 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U177 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U178 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U179 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U180 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U181 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U182 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U183 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U184 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U185 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U186 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U187 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U188 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U189 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U190 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U191 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U192 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U193 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U194 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U195 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U196 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U197 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U198 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U199 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U200 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U201 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U202 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U203 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U204 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U205 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U206 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U207 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U208 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U209 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U210 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U211 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U212 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U213 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U214 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U215 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U216 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U217 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U218 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U219 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U220 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U221 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U222 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U223 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U224 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U225 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U226 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U227 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U228 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U229 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U230 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U231 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U232 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U233 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U234 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U235 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U236 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U237 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U238 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U239 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U240 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U241 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U242 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U243 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U244 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U245 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U246 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U247 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U248 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_U249 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_32_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_33_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_34_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_35_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_36_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_37_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_38_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_39_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_40_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_41_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_42_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_43_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_44_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_45_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_46_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_47_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_48_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_49_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_50_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_51_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_52_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_53_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_54_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_55_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_56_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_57_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_58_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_59_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_60_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_61_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_62_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_63_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_64_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_65_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_66_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_67_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_68_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_69_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_70_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_71_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_72_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_73_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_74_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_75_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_76_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_77_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_78_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_79_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_80_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_81_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_82_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_83_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_84_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_85_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_86_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_87_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_88_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_89_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_90_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_91_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_92_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_93_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_94_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_95_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_96_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_97_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_98_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_99_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_100_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_101_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_102_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_103_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_104_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_105_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_106_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_107_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_108_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_109_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_110_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_111_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_112_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_113_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_114_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_115_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_116_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_117_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_118_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_119_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_120_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_121_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_122_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_123_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_124_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_125_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_126_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_127_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_128_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_129_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_130_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_131_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_132_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_133_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_134_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_135_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_136_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_137_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_138_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_139_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_140_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_141_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_142_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_143_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_144_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_145_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_146_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_147_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_148_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_149_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_150_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_151_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_152_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_153_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_154_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_155_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_156_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_157_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_158_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_159_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_160_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_161_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_162_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_163_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_164_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_165_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_166_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_167_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_168_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_169_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_170_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_171_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_172_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_173_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_174_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_175_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_176_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_177_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_178_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_179_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_180_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_181_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_182_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_183_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_184_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_185_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_186_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_187_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_188_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_189_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_190_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_191_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_192_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_193_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_194_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_195_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_196_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_197_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_198_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_199_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_200_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_201_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_202_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_203_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_204_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_205_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_206_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_207_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_208_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_209_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_210_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_211_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_212_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_213_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_214_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_215_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_216_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_217_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_218_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_219_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_220_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_221_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_222_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_223_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_224_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_225_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_226_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_227_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_228_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_229_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_230_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_231_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_232_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_233_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_234_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_235_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_236_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_237_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_238_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_239_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_decode_U3 AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U4 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U5 AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U6 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U7 NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U8 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U9 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U13 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U15 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U24 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U26 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U27 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U28 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U29 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U30 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U31 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U32 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U33 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U34 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U35 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U36 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U37 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U38 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U39 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U40 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U41 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U42 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U43 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U44 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_decode_U45 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U46 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U47 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_decode_U48 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U49 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U50 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U51 + AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U52 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U53 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U54 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U55 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U56 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U57 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U58 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U59 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U60 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U61 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U62 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U63 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U64 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U66 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U67 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U68 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U69 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U70 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U71 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U72 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U73 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U74 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U75 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U76 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U77 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U78 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U79 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U80 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U81 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U82 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U83 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U84 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U85 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U86 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U87 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U88 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U89 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U90 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U91 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U92 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U93 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U94 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U95 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U96 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U97 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U98 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U99 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U100 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U101 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U102 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U105 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U106 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U107 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U108 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U109 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U110 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U111 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U112 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U113 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U114 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_decode_U115 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U116 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U117 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U119 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U121 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U122 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U123 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U124 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U125 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U126 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U127 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U129 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U130 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U131 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U132 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U133 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U134 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U135 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U136 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U137 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U138 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U139 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U143 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U148 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U149 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U150 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U151 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U154 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U155 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U156 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U157 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U158 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U159 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U160 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U161 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U162 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U163 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U164 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U165 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U166 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U167 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U168 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U169 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U170 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U171 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U172 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U173 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U174 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U175 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U176 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U177 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U178 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U179 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U180 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U181 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U182 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U184 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U186 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U187 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U188 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U190 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U192 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U193 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U194 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U196 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U197 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U198 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U200 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U202 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U203 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U204 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U205 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U206 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U207 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U208 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U209 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U210 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U211 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U212 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U213 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U215 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U216 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U217 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U218 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U219 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U221 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U223 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U224 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U225 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U226 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U227 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U228 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U229 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U230 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U231 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U232 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U233 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U234 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U235 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U236 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U237 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U238 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U239 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U240 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U241 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U242 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U243 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U244 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U246 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U247 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U248 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U250 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U252 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U273 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U275 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U277 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_add_x_1_U2 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U3 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U4 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U5 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U6 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U7 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U8 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U9 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U10 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U11 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U12 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U13 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U14 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U15 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U16 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U17 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U18 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U19 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U20 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U21 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U22 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U23 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U24 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U25 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U26 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U27 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U28 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U29 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_f_d_reg_U2 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U3 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U4 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U5 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U6 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U7 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U8 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U9 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U10 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U11 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U12 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U13 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U14 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U15 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U16 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U17 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U18 + MX2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U19 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U20 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U21 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U22 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U23 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U24 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U25 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U26 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U27 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U28 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U29 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U30 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U31 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U32 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U33 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U34 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U35 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U36 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U37 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U38 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U39 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U40 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U41 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U42 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U43 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U44 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U45 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U46 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U47 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U48 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U49 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U50 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U51 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U52 + MX2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U53 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U54 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U55 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U56 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U57 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U58 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U59 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U60 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U61 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U62 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U63 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U64 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U65 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U66 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U67 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U68 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U69 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U70 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U71 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U72 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U73 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U74 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U75 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U76 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U77 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U78 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U79 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U80 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U81 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U82 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U83 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U84 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U85 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U86 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_32_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_33_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_34_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_35_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_36_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_37_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_38_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_39_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_40_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_41_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_42_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_43_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_44_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_45_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_46_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_47_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_48_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_49_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_50_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_51_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_52_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_53_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_54_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_55_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_56_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_57_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_58_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_59_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_60_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_61_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_62_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_63_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_64_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_65_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_66_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_67_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_68_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_69_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_70_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_U2 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U3 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U4 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U5 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U6 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U7 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U8 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U9 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U10 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U11 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U12 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U13 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U14 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U15 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U16 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U17 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U18 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U19 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U20 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U21 AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U22 INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U23 OR4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_U24 INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_U25 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_U26 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U27 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U28 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U29 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U30 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U31 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U32 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U33 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U34 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U35 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U36 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U37 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U3 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U4 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U5 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U6 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U7 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U8 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U9 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U10 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U11 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U12 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U13 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U14 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U15 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U16 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U17 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U18 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U19 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U20 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U21 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U22 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U23 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U24 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U25 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U26 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U27 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U28 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U29 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U30 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U31 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U32 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U33 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U34 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U35 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U36 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U37 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U38 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U39 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U40 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U41 + OA21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U42 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U43 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U44 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U45 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U46 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U47 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U48 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U49 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U50 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U51 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U52 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U53 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U54 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U55 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U56 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U57 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U58 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U59 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U60 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U61 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U62 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U63 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U64 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U65 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U66 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U67 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U68 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U69 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U70 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U71 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U72 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U73 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U74 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U75 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U76 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U77 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U78 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U79 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U80 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U81 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U82 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U83 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U84 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U85 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U86 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U87 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U88 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U89 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U90 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U91 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U92 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U93 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U94 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U95 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U96 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U97 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U98 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U99 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U100 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U101 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U102 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U103 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U104 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U105 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U106 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U107 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U108 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U109 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U110 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U111 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U112 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U113 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U114 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U115 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U116 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U117 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U118 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U119 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U120 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U121 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U122 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U123 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U124 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U125 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U126 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U127 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U128 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U129 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U130 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U131 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U132 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U133 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U134 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U135 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U136 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U137 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U138 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U139 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U140 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U141 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U142 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U143 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U144 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U145 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U146 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U147 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U148 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U149 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U150 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U151 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U152 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U153 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U154 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U155 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U156 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U157 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U158 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U159 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U160 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U161 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U162 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U163 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U164 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U165 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U166 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U167 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U168 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U169 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U170 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U171 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U172 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U173 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U174 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U175 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U176 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U177 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U178 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U179 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U180 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U181 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U182 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U183 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U184 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U185 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U186 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U187 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U188 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U189 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U190 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U191 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U192 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U193 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U194 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U195 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U196 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U197 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U198 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U199 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U200 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U201 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U202 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U203 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U204 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U205 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U206 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U207 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U208 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U209 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U210 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U211 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U212 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U213 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U214 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U215 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U216 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U217 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U218 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U219 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U220 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U221 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U222 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U223 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U224 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U225 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U226 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U227 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U228 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U229 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U230 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U231 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U232 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U233 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U234 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U235 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U236 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U237 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U238 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U239 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U240 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U241 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U242 + BUF_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U243 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U244 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U245 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U246 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U247 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U248 + OAI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U249 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U251 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U254 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U256 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U257 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U258 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U259 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U260 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U263 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U264 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U267 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U268 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U269 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U270 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U271 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U272 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U273 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U274 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U275 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U276 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U277 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U278 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U279 + INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U280 + NOR2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U281 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U282 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U283 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U284 + INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U285 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U286 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U292 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U296 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U297 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U299 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U303 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U304 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U305 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U306 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U307 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U308 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U309 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U310 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U311 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U312 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U313 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U314 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U315 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U316 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U317 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U318 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U319 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U320 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U321 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U322 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U323 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U324 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U325 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U326 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U327 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U328 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U329 + AO21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U330 + AO21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U331 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U332 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U333 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U334 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U335 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U336 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U337 + AOI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U338 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U339 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U340 + NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U341 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U342 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U343 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U344 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U345 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U346 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U347 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U348 + AND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U349 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U350 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U351 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U352 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U353 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U354 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U355 + AND4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U356 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U357 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U360 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U364 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U366 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U367 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U368 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U369 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U370 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U371 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U372 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U373 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U374 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U375 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U376 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U377 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U378 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U379 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U380 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U381 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U382 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U383 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U384 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U385 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U386 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U387 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U388 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U389 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U390 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U391 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U392 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U393 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U394 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U395 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U396 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U397 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U398 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U399 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U400 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U401 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U402 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U403 + OA21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U404 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U405 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U406 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U407 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U408 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U409 + OAI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U410 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U411 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U412 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U413 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U414 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U415 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U416 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U417 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U418 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U419 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U420 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U421 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U422 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U423 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U424 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U425 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U426 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U427 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U428 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U429 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U430 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U431 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U432 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U433 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U434 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U435 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U436 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U437 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U438 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U439 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U440 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U441 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U442 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U443 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U444 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U445 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U446 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U447 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U448 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U449 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U450 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U451 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U452 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U453 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U454 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U455 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U456 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U457 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U458 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U459 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U460 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U461 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U462 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U463 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U464 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U465 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U466 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U467 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U468 + NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U469 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U470 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U471 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U472 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U473 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U474 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U475 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U476 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U477 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U478 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U479 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U480 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U481 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U482 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U483 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U484 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U485 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U486 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U487 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U488 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U489 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U490 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U491 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U492 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U493 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U494 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U495 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U496 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U497 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U498 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U499 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U500 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U501 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U502 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U503 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U504 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U505 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U506 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U507 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U508 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U509 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U510 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U511 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U512 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U513 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U514 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U515 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U516 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U517 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U518 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U519 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U520 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U521 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U522 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U523 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U524 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U525 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U526 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U527 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U528 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U529 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U530 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U531 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U532 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U533 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U534 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U535 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U536 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U537 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U538 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U539 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U540 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U541 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U542 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U543 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U544 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U545 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U546 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U547 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U548 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U549 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U550 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U551 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U552 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U553 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U554 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U555 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U556 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U557 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U558 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U559 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U560 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U561 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U562 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U563 + NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U564 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U565 + AOI22BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U566 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U567 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U568 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U569 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U570 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U571 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U572 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U573 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U574 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U575 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U576 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U577 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U578 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U579 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U580 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U581 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U582 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U583 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U584 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U585 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U586 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U587 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U588 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U589 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U590 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U591 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U592 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U593 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U594 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U595 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U596 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U597 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U598 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U599 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U600 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U601 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U602 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U603 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U604 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U605 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U606 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U607 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U608 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U609 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U610 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U611 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U612 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U613 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U614 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U615 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U616 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U617 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U618 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U619 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U620 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U621 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U622 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U623 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U624 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U625 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U626 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U627 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U628 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U629 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U630 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U631 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U633 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U634 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U635 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U636 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U637 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U638 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U639 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U640 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U641 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U642 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U643 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U644 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U645 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U646 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U647 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U648 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U649 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U650 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U651 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U652 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U653 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U654 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U655 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U656 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U657 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U658 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U659 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U660 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U661 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U662 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U663 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U664 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U665 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U666 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U667 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U668 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U669 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U670 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U671 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U672 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U673 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U674 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U675 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U676 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U677 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U678 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U679 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U680 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U681 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U682 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U683 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U684 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U685 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U686 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U687 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U688 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U689 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U690 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U691 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U692 + BUF_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U693 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U694 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U695 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U696 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U697 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U698 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U699 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U700 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U701 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U702 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U703 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U704 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U705 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U706 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U707 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U708 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U709 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U710 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U711 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U712 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U713 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U714 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U715 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U716 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U717 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U718 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U719 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U720 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U721 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U722 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U723 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U724 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U725 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U726 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U727 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U728 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U729 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U730 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U731 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U732 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U733 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U734 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U735 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U736 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U737 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U738 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U739 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U740 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U741 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U742 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U743 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U744 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U745 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U746 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U747 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U748 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U749 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U750 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U751 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U752 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U753 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U754 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U755 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U756 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U757 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U758 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U759 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U760 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U761 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U762 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U763 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U764 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U765 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U766 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U767 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U768 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U769 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U770 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U771 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U772 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U773 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U774 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U775 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U776 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U777 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U778 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U779 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U780 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U781 + BUF_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U782 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U783 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U784 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U785 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U786 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U787 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U788 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U789 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U790 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U791 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U792 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U793 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U794 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U795 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U796 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U797 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U798 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U799 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U800 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U801 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U802 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U803 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U804 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U805 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U806 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U807 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U808 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U809 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U810 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U811 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U812 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U813 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U814 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U815 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U816 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U817 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U818 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U819 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U820 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U821 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U822 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U823 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U824 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U825 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U826 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U827 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U828 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U829 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U830 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U831 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U832 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U833 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U834 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U835 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U836 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U837 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U838 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U839 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U840 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U841 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U842 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U843 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U844 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U845 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U846 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U847 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U848 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U849 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U850 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U851 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U852 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U853 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U854 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U855 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U856 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U857 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U858 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U859 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U860 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U861 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U862 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U863 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U864 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U865 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U866 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U867 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U868 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U869 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U870 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U871 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U872 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U873 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U874 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U875 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U876 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U877 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U878 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U879 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U880 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U881 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U882 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U883 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U884 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U885 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U886 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U887 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U888 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U889 + OAI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U890 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U891 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U892 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U893 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U894 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U895 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U896 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U897 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U898 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U899 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U900 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U901 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U902 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U903 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U904 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U905 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U906 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U907 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U908 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U909 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U910 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U911 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U912 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U913 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U914 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U915 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U916 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U917 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U918 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U919 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U920 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U921 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U922 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U923 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U924 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U925 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U926 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U927 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U928 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U929 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U930 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U931 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U932 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U933 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U934 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U935 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U936 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U937 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U938 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U939 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U940 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U941 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U942 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U943 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U944 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U945 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U946 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U947 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U948 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U949 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U950 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U951 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U952 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U953 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U954 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U955 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U956 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U957 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U958 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U959 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U960 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U961 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U962 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U963 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U964 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U965 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U966 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U967 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U968 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U969 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U970 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U971 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U972 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U973 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U974 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U975 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U976 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U977 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U978 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U979 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U980 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U981 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U982 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U983 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U984 + AND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U985 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U986 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U987 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U988 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U989 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U990 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U991 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U992 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U993 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U994 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U995 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U996 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U997 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U998 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U999 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1000 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1001 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1002 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1003 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1004 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1005 + OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1006 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1007 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1008 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1009 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1010 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1011 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1012 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1013 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1014 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1015 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1016 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1017 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1018 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1019 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1020 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1021 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1022 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1023 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1024 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1025 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1026 + NAND3B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_front_end_vx_fetch_warp_scheduler_U1027 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1028 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1029 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1030 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1031 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1032 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1033 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1034 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1035 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1036 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1037 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1038 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1039 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1040 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1041 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1042 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1043 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1044 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1045 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1046 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1047 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1048 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1049 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1050 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1051 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1052 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1053 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1054 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1055 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1056 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1057 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1058 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1059 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1060 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1061 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1062 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1063 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1064 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1065 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1066 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1067 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1068 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1069 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1070 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1071 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1072 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1073 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1074 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1075 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1076 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1077 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1078 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1079 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1080 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1081 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1082 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1083 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1084 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1085 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1086 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1087 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1088 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1089 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1090 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1094 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1095 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1096 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1097 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1098 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1099 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1100 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1102 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1105 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1106 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1107 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1108 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1109 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1110 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1112 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1114 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1115 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1116 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1117 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1118 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1119 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1120 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1121 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1122 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1123 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1125 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1126 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1127 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1128 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1129 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1130 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1131 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1132 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1133 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1134 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1135 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1136 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1137 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1138 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1139 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1140 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1141 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1142 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1143 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1144 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1145 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1147 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1148 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1149 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1150 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1151 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1153 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1154 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1155 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1156 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1157 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1158 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1159 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1160 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1161 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1162 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1163 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1164 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1165 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1167 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1168 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1170 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1171 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1172 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1173 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1174 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1175 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1176 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1177 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1178 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1179 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1180 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1181 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1182 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1183 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1184 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1185 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1186 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1187 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1188 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1189 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1190 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1191 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1192 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1194 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1195 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1196 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1197 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1198 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1199 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1200 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1202 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1203 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1205 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1206 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1207 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1208 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1209 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1210 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1211 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1212 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1213 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1214 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1215 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1217 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1219 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1221 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1224 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1227 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1228 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1229 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1230 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1231 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1232 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1235 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1236 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1237 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1238 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1239 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1240 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1241 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1243 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1245 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1248 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1249 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1250 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1251 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1252 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1253 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1254 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1255 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1256 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1257 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1259 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1261 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1262 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1263 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1265 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1266 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1267 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1268 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1270 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1271 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1272 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1273 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1274 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1275 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1276 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1277 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1278 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1279 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1280 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1281 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1282 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1283 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1284 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1285 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1286 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1287 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1288 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1289 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1290 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1292 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1293 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1295 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1296 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1297 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1300 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1302 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1303 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1304 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1305 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1308 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1311 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1313 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1316 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1317 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1319 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1321 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1324 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1327 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1329 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1332 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1335 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1342 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1344 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1347 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1348 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1349 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1350 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1351 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1352 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1353 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1354 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1355 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1356 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1357 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1358 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1359 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1360 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1361 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1362 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1363 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1364 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1365 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1366 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1367 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1368 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1369 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1370 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1372 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1374 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1375 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1376 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1377 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1378 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1379 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1380 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1382 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1383 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1384 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1386 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1387 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1388 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1389 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1390 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1392 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1393 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1394 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1395 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1396 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1398 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1399 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1400 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1401 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1402 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1403 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1404 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1405 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1406 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1407 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1408 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1409 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1410 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1411 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1412 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1413 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1415 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1416 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1417 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1418 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1419 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1420 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1421 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1422 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1424 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1425 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1427 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1428 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1430 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1431 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1433 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1434 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1435 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1436 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1437 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1439 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1440 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1442 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1443 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1444 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1445 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1446 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1448 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1449 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1450 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1451 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1452 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1454 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1455 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1457 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1460 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1461 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1462 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1463 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1466 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1467 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1468 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1469 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1470 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1471 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1472 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1473 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1474 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1475 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1476 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1477 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1478 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1479 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1480 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1481 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1482 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1483 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1484 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1485 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1486 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1487 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1488 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1489 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1490 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1491 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1492 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1493 + OAI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1494 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1495 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1497 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1500 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1501 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1502 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1503 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1504 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1505 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1506 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1507 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1508 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1509 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1510 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1511 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1512 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1513 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1514 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1515 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1516 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1548 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1549 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1550 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1551 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1552 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1553 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1555 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1557 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1559 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1560 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1561 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1562 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1563 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1564 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1565 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1566 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1567 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1568 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1569 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1570 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1572 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1573 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1574 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1575 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1576 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1577 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1578 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1579 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1580 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1581 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1582 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1583 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1584 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1585 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1586 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1587 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1588 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1589 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1590 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1596 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1598 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1599 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1600 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1601 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1602 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1603 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1604 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1605 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1606 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1607 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1608 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1610 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1611 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1616 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1617 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1621 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1622 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1624 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1625 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1630 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1631 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1632 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1633 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1635 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1636 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1637 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1638 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1639 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1640 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1641 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1642 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1643 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1645 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1646 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1647 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1648 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1649 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1650 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1651 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1652 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1653 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1654 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1655 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1656 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1657 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1658 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1659 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1660 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1661 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1662 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1663 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1664 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1665 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1666 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1667 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1669 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1671 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1672 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1674 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1677 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1678 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1679 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1680 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1681 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1682 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1683 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1684 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1685 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1686 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1687 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1688 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1690 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1692 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1693 + NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1694 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1695 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1696 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1697 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1698 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1700 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1701 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1702 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1703 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1705 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1707 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1708 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1709 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1710 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1711 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1712 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1713 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1714 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1715 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1716 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1717 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1718 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1719 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1720 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1721 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1722 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1723 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1724 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1725 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1726 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1727 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1728 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1729 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1730 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1731 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1732 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1733 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1734 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1735 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1736 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1737 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1738 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1739 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1740 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1741 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1742 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1743 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1744 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1745 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1746 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1747 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1748 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1749 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1750 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1751 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1752 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1754 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1755 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1756 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1757 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1759 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1760 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1761 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1762 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1763 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1764 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1765 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1766 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1767 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1768 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1769 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1770 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1771 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1772 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1773 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1774 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1777 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1779 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1780 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1781 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1782 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1783 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1785 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1786 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1787 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1788 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1789 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1791 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1793 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1794 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1795 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1796 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1797 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1798 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1800 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1801 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1802 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1804 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1805 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1806 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1807 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1808 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1809 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1810 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1811 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1812 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1813 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1814 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1815 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1816 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1817 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1818 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1819 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1820 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1823 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1824 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1825 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1827 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1828 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1829 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1830 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1831 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1832 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1833 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1834 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1835 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1836 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1838 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1839 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1840 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1841 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1842 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1843 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1845 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1846 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1847 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1848 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1849 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1850 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1851 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1852 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1853 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1856 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1857 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1859 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1861 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1862 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1864 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1865 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1866 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1867 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1868 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1869 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1870 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1871 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1872 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1873 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1874 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1875 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1876 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1877 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1878 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1879 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1880 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1881 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1882 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1884 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1885 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1886 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1887 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1888 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1889 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1890 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1892 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1893 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1894 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1895 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1896 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1897 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1898 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1899 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1900 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1901 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1902 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1903 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1904 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1905 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1906 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1907 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1908 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1910 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1911 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1912 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1914 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1916 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1917 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1918 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1919 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1920 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1921 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1922 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1923 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1924 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1925 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1926 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1927 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1928 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1929 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1930 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1931 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1932 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1934 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1935 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1936 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1937 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1938 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1939 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1940 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1941 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1942 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1943 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1944 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1945 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1946 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1947 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1948 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1949 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1950 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1951 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1952 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1953 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1954 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1955 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1956 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1957 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1958 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1959 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1960 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1961 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1962 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1963 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1964 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1965 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1966 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1967 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1968 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1969 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1970 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1971 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1972 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1973 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1974 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1975 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1977 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1978 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1979 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1980 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1981 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1982 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1983 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1984 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1985 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1986 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1987 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1988 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1990 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1991 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1992 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1993 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1994 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1997 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1998 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1999 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2000 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2001 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2002 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2003 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2004 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2005 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2006 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2007 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2008 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2009 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2010 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2011 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2012 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2013 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2014 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2015 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2016 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2017 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2018 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2019 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2020 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2021 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2023 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2024 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2025 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2026 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2027 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2028 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2029 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2030 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2031 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2032 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2033 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2034 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2035 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2036 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2037 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2038 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2039 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2040 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2041 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2042 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2043 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2044 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2045 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2046 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2047 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2048 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2049 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2050 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2051 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2052 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2053 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2054 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2055 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2056 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2057 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2058 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2059 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2060 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2061 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2062 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2063 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2064 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2065 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2066 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2067 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2068 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2069 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2070 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2071 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2072 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2073 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2074 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2075 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2076 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2077 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2078 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2079 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2080 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2081 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2082 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2083 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2084 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2085 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2086 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2087 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2088 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2089 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2090 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2091 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2092 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2093 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2094 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2095 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2096 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2097 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2098 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2099 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2100 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2102 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2105 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2106 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2107 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2108 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2109 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2110 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2111 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2112 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2113 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2118 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2123 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2127 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2132 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2133 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2134 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2136 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2137 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2138 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2139 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2140 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2141 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2142 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2143 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2147 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2150 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2151 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2155 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2156 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2159 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2160 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2161 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2164 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2165 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2170 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2171 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2174 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2175 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2176 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2177 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2178 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2181 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2182 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2183 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2184 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2185 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2186 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2187 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2188 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2189 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2190 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2191 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2192 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2193 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2194 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2195 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2196 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2197 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2198 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2199 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2201 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2202 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2203 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2205 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2206 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2209 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2210 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2211 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2212 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2213 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2214 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2215 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2216 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2217 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2218 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2219 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2220 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2221 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2222 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2223 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2224 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2225 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2227 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2228 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2229 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2230 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2231 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2232 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2233 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2234 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2235 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2236 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2237 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2238 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2239 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2240 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2241 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2243 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2245 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2246 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2247 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2248 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2249 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2250 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2251 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2252 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2253 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2254 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2255 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2256 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2258 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2259 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2261 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2262 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2263 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2264 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2266 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2267 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2268 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2269 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2271 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2272 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2273 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2275 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2277 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2278 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2280 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2281 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2282 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2284 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2285 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2286 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2287 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2288 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2289 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2292 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2295 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2296 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2297 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2299 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2303 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2307 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2308 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2309 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2310 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2311 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2312 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2313 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2314 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2315 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2316 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2317 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2319 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2320 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2321 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2323 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2324 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2326 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2327 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2328 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2330 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2331 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2332 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2334 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2335 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2336 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2338 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2339 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2340 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2341 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2342 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2343 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2344 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2345 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2346 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2347 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2348 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2349 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2350 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2351 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2352 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2353 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2354 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2355 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2356 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2357 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2358 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2359 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2360 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2361 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2362 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2363 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2364 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2365 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2366 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2367 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2368 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2369 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2370 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2371 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2372 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2373 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2377 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2380 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2383 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2384 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2385 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2387 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2388 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2389 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2390 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2391 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2392 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2393 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2395 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2396 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2397 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2398 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2399 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2400 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2401 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2402 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2403 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2404 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2405 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2406 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2407 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2408 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2409 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2410 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2411 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2412 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2414 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2415 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2416 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2417 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2418 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2419 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2420 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2421 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2422 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2423 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2424 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2425 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2426 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2427 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2428 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2429 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2430 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2431 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2432 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2433 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2434 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2435 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2436 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2437 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2438 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2439 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2440 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2441 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2442 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2443 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2444 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2445 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2446 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2447 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2448 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2449 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2450 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2451 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2452 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2453 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2454 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2455 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2456 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2457 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2458 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2459 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2460 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2461 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2462 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2463 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2464 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2465 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2466 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2467 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2468 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2469 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2470 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2471 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2472 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2473 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2474 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2475 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U1 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U2 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U6 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U9 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U10 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U11 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U3 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U4 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U6 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U9 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U10 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U11 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U13 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U14 + OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U12 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U14 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U15 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U17 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U18 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U19 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U20 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U22 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U24 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U26 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U27 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U28 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U29 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U30 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U31 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U32 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U33 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U34 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U36 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U38 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U39 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U40 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U42 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U43 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U45 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U46 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U47 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U77 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U142 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U147 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U148 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U150 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U152 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U162 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U164 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U166 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U168 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U170 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U172 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U173 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U175 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U177 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U179 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U181 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U187 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U192 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U194 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U196 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U198 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U200 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U202 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U204 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U206 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U208 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U210 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U11 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U13 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U14 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U16 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U17 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U18 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U19 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U20 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U21 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U22 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U23 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U24 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U25 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U26 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U27 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U28 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U29 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U30 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U31 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U32 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U37 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U38 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U39 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U40 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U42 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U43 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U45 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U46 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U47 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U77 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U110 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U147 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U148 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U150 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U152 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U162 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U164 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U166 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U168 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U170 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U172 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U174 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U176 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U178 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U180 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U182 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U184 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U186 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U188 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U190 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U192 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U194 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U196 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U198 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U200 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U202 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U204 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U206 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U208 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U210 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U12 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U15 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U16 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U17 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U19 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U20 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U22 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U24 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U26 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U27 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U28 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U29 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U30 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U31 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U32 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U33 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U34 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U36 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U38 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U39 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U40 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U41 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U42 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U43 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U44 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U45 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U46 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U47 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U77 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U78 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U143 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U148 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U149 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U151 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U153 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U157 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U159 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U161 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U163 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U165 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U167 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U169 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U171 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U173 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U175 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U177 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U179 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U181 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U187 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U193 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U197 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U205 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U207 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U209 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U210 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U3 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U9 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U16 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U17 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U19 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U20 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U22 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U24 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U25 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U26 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U27 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U28 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U29 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U30 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U31 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U32 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U37 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U39 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U40 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U41 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U42 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U43 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U44 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U46 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U47 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U77 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U78 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U143 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U148 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U149 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U151 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U153 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U155 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U162 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U164 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U166 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U168 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U170 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U172 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U174 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U176 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U178 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U180 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U182 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U184 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U186 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U188 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U190 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U193 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U197 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U205 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U206 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U208 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U210 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U8 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U9 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U16 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U17 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U19 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U20 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U22 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U24 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U26 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U27 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U28 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U29 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U30 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U31 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U32 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U33 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U34 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U37 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U39 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U40 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U41 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U42 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U43 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U45 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U46 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U47 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U77 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U142 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U147 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U148 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U150 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U152 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U161 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U163 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U165 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U167 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U169 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U171 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U173 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U175 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U177 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U179 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U181 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U187 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U193 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U197 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U205 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U207 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U209 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U211 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U13 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U15 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U18 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U19 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U20 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U21 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U22 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U23 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U24 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U25 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U26 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U27 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U28 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U29 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U30 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U31 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U32 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U37 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U39 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U40 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U41 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U42 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U43 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U44 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U45 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U46 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U47 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U77 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U142 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U147 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U148 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U150 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U152 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U162 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U164 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U166 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U168 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U170 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U172 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U174 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U176 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U178 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U180 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U182 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U184 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U186 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U188 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U190 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U193 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U197 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U205 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U206 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U208 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U210 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U3 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U8 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U13 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U15 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U18 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U19 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U20 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U21 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U22 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U23 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U24 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U25 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U26 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U27 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U28 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U29 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U30 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U31 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U32 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U37 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U39 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U40 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U41 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U42 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U43 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U44 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U46 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U47 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U77 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U78 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U143 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U148 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U149 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U150 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U152 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U162 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U164 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U166 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U168 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U170 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U172 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U174 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U176 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U178 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U179 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U181 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U187 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U193 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U197 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U205 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U207 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U209 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U211 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U213 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U215 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U217 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U219 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U6 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U7 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U12 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U14 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U15 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U17 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U18 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U19 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U20 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U22 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U24 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U26 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U27 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U28 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U29 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U30 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U31 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U32 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U33 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U34 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U36 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U38 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U39 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U40 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U42 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U43 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U45 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U46 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U47 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U49 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U52 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U53 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U54 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U55 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U56 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U57 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U61 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U63 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U64 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U65 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U66 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U67 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U68 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U69 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U70 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U71 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U72 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U73 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U74 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U75 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U76 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U77 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U110 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U147 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U148 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U150 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U152 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U154 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U156 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U158 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U160 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U162 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U164 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U166 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U168 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U170 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U171 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U173 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U175 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U177 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U179 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U181 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U187 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U193 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U197 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U203 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U205 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U207 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U208 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U210 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U212 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U216 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U218 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U220 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_num_visible_U1 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_num_visible_U2 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_num_visible_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_num_visible_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_num_visible_U6 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U9 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U10 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U11 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__0_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__21_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__22_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__23_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__25_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__26_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__28_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__29_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__30_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +-------------------------------------------------------------------------------- +Total 132902 cells 599669.219882 +1 +report_reference + +**************************************** +Report : reference +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:41 2019 +**************************************** + +Attributes: + b - black box (unknown) + bo - allows boundary optimization + d - dont_touch + mo - map_only + h - hierarchical + n - noncombinational + r - removable + s - synthetic operator + u - contains unmapped logic + +Reference Library Unit Area Count Total Area Attributes +----------------------------------------------------------------------------- +ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 3721 10247.633808 r +ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 211 376.001989 r +AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 733 593.730002 +AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 69 55.890000 +AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 64 51.840000 +AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 553 447.930001 +AND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3 2.916000 +AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 47 45.684000 +AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 40 38.880000 +AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 83 80.676000 +AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 78 113.723996 +AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 21 34.020000 +AND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 3 5.832000 +AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 24 62.208000 +AND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 1 2.592000 +AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 9 29.160000 +AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 58 56.376000 +AND3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +AND3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +AND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +AND3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 2 3.888000 +AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 144 163.295992 +AND4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 6 6.804000 +AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 57 55.404000 +AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 323 313.956001 +AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 41 53.136000 +AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 156 202.176001 +AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 74 143.856000 +AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 98 222.263989 +AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 3 9.720000 +AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 391 380.052001 +AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +AO21A1AI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 14 13.608000 +AO21A1AI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 12 19.440000 +AO21A1AI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 25 40.500000 +AO21A1AI2_X3M_A12TUL_C35 + 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+ 1.296000 39 50.544000 +AO22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 1 1.458000 +AO22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 3 6.804000 +AO22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 1 2.430000 +AO22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 1 4.050000 +AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 61 69.173997 +AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 4 4.536000 +AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 173 196.181990 +AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 70 113.400000 +AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 388 628.560002 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 6 5.832000 +AOI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 4 3.888000 +AOI31_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 3 5.346000 +AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 4 9.072000 +AOI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 1 3.078000 +AOI31_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 1 4.374000 +AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 346 336.312001 +AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 28 27.216000 +AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 5 8.100000 +AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 1 2.268000 +BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 10 6.480000 +BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 11 8.910000 +BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 7 7.938000 +BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 14 18.144000 +BUFH_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 4 6.480000 +BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 24 46.656000 +BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 6 14.580000 +BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 19 58.482001 +BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 108 69.984000 +BUF_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 13 8.424000 +BUF_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 21 13.608000 +BUF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 1 0.810000 +BUF_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 39 31.590000 +BUF_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 7 5.670000 +BUF_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 10 9.720000 +BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 6 6.804000 +BUF_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +BUF_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 4 5.832000 +BUF_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 23 37.260000 +BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 17 33.048000 +BUF_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 17 38.555998 +BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 20 64.800000 +CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 135 153.089992 +CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 21 40.824000 +CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 86 111.456000 +DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 904 2489.615953 n +DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 1741 5922.881914 n +DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 8 25.920000 n +DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 1 3.240000 n +DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 214 728.027989 n +DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 2 7.128000 n +DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 6 22.356000 n +DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 8 32.400002 n +DFFSQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 2 6.480000 n +DFFSQN_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 1 3.564000 n +INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 13854 6733.044020 +INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 3420 1662.120005 +INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 570 277.020001 +INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 240 116.640000 +INV_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 2574 1250.964004 +INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 79 51.192000 +INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 2 1.296000 +INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 23 14.904000 +INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 11 7.128000 +INV_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 620 401.760001 +INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 25 20.250000 +INV_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 2 1.620000 +INV_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 141 114.210000 +INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 14 13.608000 +INV_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 128 124.416000 +INV_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 61 69.173997 +INV_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 130 168.480000 +INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 94 152.280000 +INV_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 81 144.341996 +INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 70 147.419996 +INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 24 73.872002 +LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 129 208.980001 n +MX2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 3 4.860000 +MX2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 1 1.944000 +MX2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 37 71.928000 +MX2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 1 3.078000 +MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 690 782.459961 +MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 99 128.304000 +MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 423 616.733977 +MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1073 1912.085942 +MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 893 1880.657952 +MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 342 831.060023 +MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 23 74.520000 +MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 514 749.411972 +MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 1634 2382.371910 +MXT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 88 142.560000 +MXT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 46 81.971997 +MXT2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1 1.782000 +MXT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 90 160.379995 +MXT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 6 15.552000 +MXT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 2 5.508000 +MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 1 3.726000 +NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 373 302.130001 +NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 14 15.875999 +NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 53 60.101997 +NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 8 11.664000 +NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 2 5.184000 +NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 15 12.150000 +NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 184 149.040000 +NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 16 18.143999 +NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 65 73.709996 +NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 21 30.617999 +NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 24 42.767999 +NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 29 75.168000 +NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 12 38.880000 +NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 9712 6293.376019 +NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 554 358.992001 +NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 1706 1105.488003 +NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 1683 1090.584003 +NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 4646 3010.608009 +NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 453 440.316001 +NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 791 768.852002 +NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 586 569.592002 +NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1284 1248.048004 +NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 29 37.584000 +NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 24 31.104000 +NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 19 30.780000 +NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 14 22.680000 +NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 14 31.751998 +NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 15 34.019998 +NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 10 29.159999 +NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 2 5.832000 +NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 18 17.496000 +NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 16 15.552000 +NAND3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 14 18.144000 +NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 9 17.496000 +NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 2 4.536000 +NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 2 6.480000 +NAND3B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +NAND3B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 2 3.888000 +NAND3B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 1 3.726000 +NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 7 6.804000 +NAND3XXB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +NAND3XXB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 1 1.458000 +NAND3XXB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 2 2.916000 +NAND3XXB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 1 1.944000 +NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 139 112.590000 +NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 2 1.620000 +NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 22 17.820000 +NAND3_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 14 18.144000 +NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 10 17.819999 +NAND3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1 1.782000 +NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 1 3.240000 +NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 50 56.699997 +NAND4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +NAND4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1 1.782000 +NAND4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 6 10.692000 +NAND4BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 2 8.748000 +NAND4B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 4 4.536000 +NAND4XXXB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 1 1.944000 +NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 252 244.944001 +NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 12 11.664000 +NAND4_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 1 1.620000 +NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 8 12.960000 +NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 1 2.268000 +NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 543 439.830001 +NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 20 16.200000 +NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 80 64.800000 +NOR2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 6 6.804000 +NOR2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 54 61.235997 +NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 7 10.206000 +NOR2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 4 10.368000 +NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 419 339.390001 +NOR2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 3 2.430000 +NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 100 81.000000 +NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 10 11.339999 +NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 29 32.885998 +NOR2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 3 4.374000 +NOR2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 2 3.564000 +NOR2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 1 2.592000 +NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 2320 1503.360004 +NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 89 57.672000 +NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 628 406.944001 +NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 4912 3182.976009 +NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 1813 1174.824003 +NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 82 79.704000 +NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 295 286.740001 +NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3455 3358.260010 +NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 29 28.188000 +NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 2328 2262.816007 +NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 199 257.904001 +NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 231 299.376001 +NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 15 24.300000 +NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 12 19.440000 +NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 14 31.751998 +NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 5 11.339999 +NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 3 8.748000 +NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 59 57.348000 +NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 4 3.888000 +NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 42 40.824000 +NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 6 7.776000 +NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 6 7.776000 +NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 2 3.888000 +NOR3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 3 6.804000 +NOR3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 4 12.960000 +NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 252 204.120001 +NOR3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 2 1.620000 +NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 10 8.100000 +NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 7 5.670000 +NOR3_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 27 34.992000 +NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 13 16.848000 +NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 23 29.808000 +NOR3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 2 3.564000 +NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 69 78.245996 +NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 4 4.536000 +NOR4BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 4 7.128000 +NOR4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 3 5.346000 +OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 5 4.860000 +OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 76 73.872000 +OA1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 45 58.320000 +OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 332 430.272001 +OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 13 25.272000 +OA1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 6 13.607999 +OA1B2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 1 4.212000 +OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 283 275.076001 +OA21A1OI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 16 15.552000 +OA21A1OI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 1 1.620000 +OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 7 11.340000 +OA21A1OI2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 17 38.555998 +OA21A1OI2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 12 34.991999 +OA21A1OI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 16 67.391998 +OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 35 34.020000 +OA21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 117 113.724000 +OA21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 30 38.880000 +OA21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 2 3.888000 +OA21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 1 3.240000 +OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 23 26.081999 +OA21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 23 26.081999 +OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 65 73.709996 +OA21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 45 58.320000 +OA21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 12 15.552000 +OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 27 52.488000 +OA21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 4 8.424000 +OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 5 17.010000 +OA21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 2 8.424000 +OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 10 12.960000 +OA22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +OA22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +OA22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 2 2.916000 +OA22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 2 4.860000 +OA22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 5 20.250001 +OA22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.022000 1 5.022000 +OA211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +OA211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1 1.296000 +OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 28 31.751998 +OAI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 4 4.536000 +OAI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 22 24.947999 +OAI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 6 9.720000 +OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 38 61.560000 +OAI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 6 12.636000 +OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 1 2.754000 +OAI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 3 11.178000 +OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 5 5.670000 +OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 15 17.009999 +OAI21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 2 3.240000 +OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 8 12.960000 +OAI21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 5 10.530000 +OAI21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 6 15.552000 +OAI21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 2 7.452000 +OAI21B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 1 4.698000 +OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 3496 2831.760008 +OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 2112 1710.720005 +OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 3543 2869.830008 +OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1148 1487.808004 +OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1752 2270.592007 +OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 353 629.045981 +OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 92 208.655990 +OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 30 97.200000 +OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 5 21.059999 +OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 193 250.128001 +OAI22BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 3 5.346000 +OAI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 2 3.564000 +OAI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 1 2.592000 +OAI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 3 9.234000 +OAI22BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 2 8.748000 +OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 2584 2511.648007 +OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 10 9.720000 +OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 45 72.900000 +OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 71 115.020000 +OAI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 11 24.947999 +OAI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 9 26.243999 +OAI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 7 29.483999 +OAI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 1 5.508000 +OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 55 53.460000 +OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 2 1.944000 +OAI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +OAI31_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1 1.782000 +OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 2 3.564000 +OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 1 2.268000 +OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 2 6.156000 +OAI31_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 2 8.748000 +OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 963 936.036003 +OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 6 5.832000 +OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 50 48.600000 +OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 1 1.620000 +OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 26 42.120000 +OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 8 18.143999 +OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 121 98.010000 +OR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 606 490.860001 +OR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 5 4.860000 +OR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 86 83.592000 +OR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 57 83.105997 +OR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 7 11.340000 +OR2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 15 38.880000 +OR2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 2 7.128000 +OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 50 48.600000 +OR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 27 39.365999 +OR4_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 3 4.374000 +OR4_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1 1.782000 +OR4_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 4 7.128000 +OR4_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 1 3.078000 +TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 25 16.200000 +TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 46 29.808000 +XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1513 1960.848006 +XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 2302 2983.392009 +XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 2129 2759.184008 +XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 16 31.104000 +XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 139 270.216001 +XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 23 63.341999 +XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 6 19.440000 +XNOR3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 1 2.430000 +XNOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 3 7.290000 +XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 2998 3885.408011 +XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 572 741.312002 +XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 505 654.480002 +XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 18 34.992000 +XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 114 221.616001 +XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 17 46.817999 +XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 5 16.200000 +XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 6 14.580000 +rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 16 140488.187500 b, d +rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 8 113256.781250 b, d +rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 8 41510.566406 b, d +rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 8 170607.031250 b, d +----------------------------------------------------------------------------- +Total 437 references 599669.219882 +1 +report_port + +**************************************** +Report : port +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:41 2019 +**************************************** + + + +Attributes: + i - ideal_network + + Pin Wire Max Max Connection +Port Dir Load Load Trans Cap Class Attrs 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+i_m_readdata_7__2__7_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__8_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__9_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__10_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__11_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__12_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__13_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__14_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__15_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__16_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__17_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__18_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__19_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__20_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__21_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__22_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__23_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__24_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__25_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__26_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__27_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__28_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__29_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__30_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__2__31_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__0_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__1_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__2_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__3_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__4_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__5_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__6_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__7_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__8_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__9_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__10_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__11_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__12_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__13_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__14_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__15_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__16_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__17_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__18_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__19_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__20_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__21_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__22_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__23_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__24_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__25_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__26_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__27_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__28_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__29_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__30_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_7__3__31_ + in 0.0000 0.0000 -- -- -- +i_m_ready in 0.0000 0.0000 -- -- -- +icache_response_instruction_0_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_1_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_2_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_3_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_4_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_5_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_6_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_7_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_8_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_9_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_10_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_11_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_12_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_13_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_14_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_15_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_16_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_17_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_18_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_19_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_20_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_21_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_22_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_23_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_24_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_25_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_26_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_27_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_28_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_29_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_30_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_31_ + in 0.0000 0.0000 -- -- -- +reset in 0.0000 0.0000 -- -- -- +icache_request_pc_address_0_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_1_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_2_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_3_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_4_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_5_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_6_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_7_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_8_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_9_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_10_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_11_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_12_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_13_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_14_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_15_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_16_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_17_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_18_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_19_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_20_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_21_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_22_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_23_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_24_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_25_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_26_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_27_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_28_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_29_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_30_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_31_ + out 0.0000 0.0000 -- -- -- +io_data_0_ out 0.0000 0.0000 -- -- -- +io_data_1_ out 0.0000 0.0000 -- -- -- +io_data_2_ out 0.0000 0.0000 -- -- -- +io_data_3_ out 0.0000 0.0000 -- -- -- +io_data_4_ out 0.0000 0.0000 -- -- -- +io_data_5_ out 0.0000 0.0000 -- -- -- +io_data_6_ out 0.0000 0.0000 -- -- -- +io_data_7_ out 0.0000 0.0000 -- -- -- +io_data_8_ out 0.0000 0.0000 -- -- -- +io_data_9_ out 0.0000 0.0000 -- -- -- +io_data_10_ out 0.0000 0.0000 -- -- -- +io_data_11_ out 0.0000 0.0000 -- -- -- +io_data_12_ out 0.0000 0.0000 -- -- -- +io_data_13_ out 0.0000 0.0000 -- -- -- +io_data_14_ out 0.0000 0.0000 -- -- -- +io_data_15_ out 0.0000 0.0000 -- -- -- +io_data_16_ out 0.0000 0.0000 -- -- -- +io_data_17_ out 0.0000 0.0000 -- -- -- +io_data_18_ out 0.0000 0.0000 -- -- -- +io_data_19_ out 0.0000 0.0000 -- -- -- +io_data_20_ out 0.0000 0.0000 -- -- -- +io_data_21_ out 0.0000 0.0000 -- -- -- +io_data_22_ out 0.0000 0.0000 -- -- -- +io_data_23_ out 0.0000 0.0000 -- -- -- +io_data_24_ out 0.0000 0.0000 -- -- -- +io_data_25_ out 0.0000 0.0000 -- -- -- +io_data_26_ out 0.0000 0.0000 -- -- -- +io_data_27_ out 0.0000 0.0000 -- -- -- +io_data_28_ out 0.0000 0.0000 -- -- -- +io_data_29_ out 0.0000 0.0000 -- -- -- +io_data_30_ out 0.0000 0.0000 -- -- -- +io_data_31_ out 0.0000 0.0000 -- -- -- +io_valid out 0.0000 0.0000 -- -- -- +o_m_evict_addr_0_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_1_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_2_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_3_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_4_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_5_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_6_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_7_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_8_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_9_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_10_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_11_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_12_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_13_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_14_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_15_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_16_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_17_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_18_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_19_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_20_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_21_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_22_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_23_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_24_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_25_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_26_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_27_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_28_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_29_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_30_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_31_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_0_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_1_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_2_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_3_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_4_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_5_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_6_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_7_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_8_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_9_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_10_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_11_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_12_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_13_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_14_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_15_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_16_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_17_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_18_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_19_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_20_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_21_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_22_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_23_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_24_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_25_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_26_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_27_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_28_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_29_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_30_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_31_ + out 0.0000 0.0000 -- -- -- +o_m_read_or_write + out 0.0000 0.0000 -- -- -- +o_m_valid out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__17_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__28_ + out 0.0000 0.0000 -- -- -- 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0.0000 -- -- -- +o_m_writedata_0__1__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__17_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__1_ + out 0.0000 0.0000 -- -- -- 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0.0000 0.0000 -- -- -- +o_m_writedata_0__2__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__6_ + out 0.0000 0.0000 -- -- -- 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0.0000 0.0000 -- -- -- +o_m_writedata_0__3__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__11_ + out 0.0000 0.0000 -- -- -- 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out 0.0000 0.0000 -- -- -- +o_m_writedata_1__0__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__1__16_ + out 0.0000 0.0000 -- -- -- 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0.0000 0.0000 -- -- -- +o_m_writedata_1__2__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__17_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_1__2__21_ + out 0.0000 0.0000 -- -- -- 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0.0000 -- -- -- +o_m_writedata_7__3__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_7__3__31_ + out 0.0000 0.0000 -- -- -- +out_ebreak out 0.0000 0.0000 -- -- -- + +1 +report_power +Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) +Warning: Design has unannotated primary inputs. (PWR-414) +Warning: Design has unannotated sequential cell outputs. (PWR-415) +Warning: Design has unannotated black box outputs. (PWR-428) + +**************************************** +Report : power + -analysis_effort low +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 16:15:54 2019 +**************************************** + + +Library(s) Used: + + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db) + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (File: /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db) + + +Operating Conditions: ssg_typical_max_0p81v_m40c Library: sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c +Wire Load Model Mode: top + +Design Wire Load Model Library +------------------------------------------------ +Vortex Small sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + + +Global Operating Voltage = 0.81 +Power-specific unit information : + Voltage Units = 1V + Capacitance Units = 1.000000pf + Time Units = 1ns + Dynamic Power Units = 1mW (derived from V,C,T units) + Leakage Power Units = 1uW + + + Cell Internal Power = 16.5394 mW (88%) + Net Switching Power = 2.2941 mW (12%) + --------- +Total Dynamic Power = 18.8335 mW (100%) + +Cell Leakage Power = 53.7742 uW + + + Internal Switching Leakage Total +Power Group Power Power Power Power ( % ) Attrs +-------------------------------------------------------------------------------------------------- +io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) +memory 14.6405 3.5469e-02 34.8456 14.7108 ( 77.89%) +black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) +clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%) +register 0.8597 5.2109e-02 0.8086 0.9126 ( 4.83%) +sequential 4.3395e-04 0.0000 3.0847e-02 4.6480e-04 ( 0.00%) +combinational 1.0389 2.2064 18.0881 3.2633 ( 17.28%) +-------------------------------------------------------------------------------------------------- +Total 16.5394 mW 2.2940 mW 53.7732 uW 18.8872 mW +1 +write -hierarchy -format verilog -output Vortex.netlist.v +Writing verilog file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/Vortex.netlist.v'. +Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4) +1 +remove_ideal_network [get_ports clk] +1 +set_propagated_clock [get_ports clk] +Information: set_input_delay values are added to the propagated clock skew. (TIM-113) +1 +write_sdc -version 1.9 Vortex.sdc +1 +write_file -format ddc -output Vortex.ddc +Writing ddc file 'Vortex.ddc'. +1 +exit + +Thank you...