area optimization bundle
This commit is contained in:
16
hw/rtl/cache/VX_miss_resrv.v
vendored
16
hw/rtl/cache/VX_miss_resrv.v
vendored
@@ -81,14 +81,14 @@ module VX_miss_resrv #(
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reg [MSHR_SIZE-1:0] valid_table_x;
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reg [MSHR_SIZE-1:0] ready_table_x;
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wire [MSHR_SIZE-1:0] addr_match;
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wire [MSHR_SIZE-1:0] addr_matches;
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wire allocate_fire = allocate_valid && allocate_ready;
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wire dequeue_fire = dequeue_valid && dequeue_ready;
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for (genvar i = 0; i < MSHR_SIZE; ++i) begin
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assign addr_match[i] = (i != lookup_id) && valid_table[i] && (addr_table[i] == lookup_addr);
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assign addr_matches[i] = (addr_table[i] == lookup_addr);
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end
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always @(*) begin
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@@ -98,12 +98,12 @@ module VX_miss_resrv #(
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valid_table_x[dequeue_id] = 0;
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end
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if (lookup_replay) begin
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ready_table_x |= addr_match;
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ready_table_x |= addr_matches;
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end
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end
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VX_lzc #(
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.WIDTH (MSHR_SIZE)
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.N (MSHR_SIZE)
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) dequeue_sel (
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.in_i (valid_table_x & ready_table_x),
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.cnt_o (dequeue_id_x),
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@@ -111,7 +111,7 @@ module VX_miss_resrv #(
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);
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VX_lzc #(
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.WIDTH (MSHR_SIZE)
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.N (MSHR_SIZE)
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) allocate_sel (
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.in_i (~valid_table_n),
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.cnt_o (allocate_id_n),
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@@ -189,7 +189,11 @@ module VX_miss_resrv #(
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assign dequeue_id = dequeue_id_r;
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assign dequeue_addr = addr_table[dequeue_id_r];
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assign lookup_match = (| addr_match);
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wire [MSHR_SIZE-1:0] lookup_entries;
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for (genvar i = 0; i < MSHR_SIZE; ++i) begin
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assign lookup_entries[i] = (i != lookup_id);
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end
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assign lookup_match = |(lookup_entries & valid_table & addr_matches);
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`UNUSED_VAR (lookup_valid)
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