critical path optimization - fpga fmax @4c = ~212 mhz
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@@ -56,29 +56,25 @@ module VX_generic_queue #(
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always @(posedge clk) begin
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if (reset) begin
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empty_r <= 1;
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full_r <= 0;
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empty_r <= 1;
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full_r <= 0;
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used_r <= 0;
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end else begin
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if (push) begin
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assert(!full);
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if (!pop) begin
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empty_r <= 0;
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if (used_r == ADDRW'(SIZE-1)) begin
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full_r <= 1;
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end
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assert(!push || !full);
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assert(!pop || !empty);
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if (push && !pop) begin
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empty_r <= 0;
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if (used_r == ADDRW'(SIZE-1)) begin
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full_r <= 1;
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end
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end
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if (pop) begin
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assert(!empty);
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if (!push) begin
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full_r <= 0;
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if (used_r == ADDRW'(1)) begin
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empty_r <= 1;
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end;
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end
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if (pop && !push) begin
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full_r <= 0;
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if (used_r == ADDRW'(1)) begin
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empty_r <= 1;
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end;
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end
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used_r <= used_r + (ADDRW'(push) - ADDRW'(pop));
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used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop)));
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end
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end
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