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minor update

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This commit is contained in:
Blaise Tine
2020-12-26 14:47:41 -08:00
parent 33c431ed44
commit b2b8f190dd
9 changed files with 199 additions and 198 deletions
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187
hw/rtl/libs/VX_shift_register.v
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@@ -1,81 +1,16 @@
`include "VX_platform.vh"
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (RESETW != 0) begin
if (RESETW == DATAW) begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end else begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr_wr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[DATAW-1:DATAW-RESETW]),
.data_out (data_out[DATAW-1:DATAW-RESETW])
);
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr_nr (
.clk (clk),
.enable (enable),
.data_in (data_in[DATAW-RESETW-1:0]),
.data_out (data_out[DATAW-RESETW-1:0])
);
end
end else begin
`UNUSED_VAR (reset)
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr (
.clk (clk),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end
endmodule
module VX_shift_register_nr #(
parameter DATAW = 1,
parameter DEPTH = 1
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),
parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
) (
input wire clk,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
input wire clk,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
reg [DATAW-1:0] entries [DEPTH-1:0];
@@ -87,19 +22,24 @@ module VX_shift_register_nr #(
end
end
assign data_out = entries [DEPTH-1];
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [ TAPS[i*DEPTHW+:DEPTHW] ];
end
endmodule
module VX_shift_register_wr #(
parameter DATAW = 1,
parameter DEPTH = 1
parameter DATAW = 1,
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),
parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
reg [DEPTH-1:0][DATAW-1:0] entries;
@@ -126,8 +66,89 @@ module VX_shift_register_wr #(
end
end
end
end
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [ TAPS[i*DEPTHW+:DEPTHW] ];
end
endmodule
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),
parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
if (RESETW != 0) begin
if (RESETW == DATAW) begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end else begin
VX_shift_register_wr #(
.DATAW (RESETW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr_wr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[DATAW-1:DATAW-RESETW]),
.data_out (data_out[DATAW-1:DATAW-RESETW])
);
VX_shift_register_nr #(
.DATAW (DATAW-RESETW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr_nr (
.clk (clk),
.enable (enable),
.data_in (data_in[DATAW-RESETW-1:0]),
.data_out (data_out[DATAW-RESETW-1:0])
);
end
end else begin
`UNUSED_VAR (reset)
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr (
.clk (clk),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end
assign data_out = entries [DEPTH-1];
endmodule