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ICache_In_Place
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Lyons, Ethan Tyler
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GitHub Enterprise
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7e62e02b7c
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b0f685c2e2
130
rtl/Vortex.v
130
rtl/Vortex.v
@@ -18,17 +18,29 @@ module Vortex
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// Req
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output reg [31:0] o_m_read_addr,
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output reg [31:0] o_m_evict_addr,
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output reg o_m_valid,
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output reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
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output reg o_m_read_or_write,
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// Rsp
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input wire [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
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input wire i_m_ready,
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output wire out_ebreak
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// Req D Mem
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output reg [31:0] o_m_read_addr_d,
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output reg [31:0] o_m_evict_addr_d,
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output reg o_m_valid_d,
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output reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
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output reg o_m_read_or_write_d,
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// Rsp D Mem
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input wire [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
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input wire i_m_ready_d,
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// Req I Mem
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output reg [31:0] o_m_read_addr_i,
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output reg [31:0] o_m_evict_addr_i,
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output reg o_m_valid_i,
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output reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
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output reg o_m_read_or_write_i,
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// Rsp I Mem
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input wire [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
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input wire i_m_ready_i,
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output wire out_ebreak
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);
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@@ -49,34 +61,85 @@ assign io_data = temp_io_data;
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VX_dram_req_rsp_inter #(
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.NUMBER_BANKS(`DCACHE_BANKS),
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.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp();
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.NUMBER_BANKS(`DCACHE_BANKS),
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.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp();
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assign o_m_read_addr = VX_dram_req_rsp.o_m_read_addr;
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assign o_m_evict_addr = VX_dram_req_rsp.o_m_evict_addr;
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assign o_m_valid = VX_dram_req_rsp.o_m_valid;
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assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
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VX_icache_response_inter icache_response_fe();
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VX_icache_request_inter icache_request_fe();
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VX_dram_req_rsp_inter #(
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.NUMBER_BANKS(`ICACHE_BANKS),
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.NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp_icache();
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assign VX_dram_req_rsp.i_m_ready = i_m_ready;
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//assign icache_response_fe.instruction = icache_response_instruction;
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assign icache_request_pc_address = icache_request_fe.pc_address;
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// Need to fix this so that it is only 1 set of outputs
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// o_m Values
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// L2 Cache
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/*
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assign VX_L2cache_req.out_cache_driver_in_valid = VX_dram_req_rsp.o_m_valid || VX_dram_req_rsp_icache.o_m_valid; // Ask about this (width)
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// Ask about the adress
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assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? icache_request_fe.pc_address: VX_dcache_req.out_cache_driver_in_address;
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//assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_read_addr: VX_dram_req_rsp.o_m_read_addr;
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//assign VX_L2cache_req.out_cache_driver_in_address = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_evict_addr : VX_dram_req_rsp.o_m_evict_addr;
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assign VX_L2cache_req.out_cache_driver_in_mem_read = (VX_dram_req_rsp_icache.o_m_valid) ? (VX_dram_req_rsp_icache.o_m_read_or_write ? icache_request_fe.out_cache_driver_in_mem_write : icache_request_fe.out_cache_driver_in_mem_read)
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: (VX_dram_req_rsp.o_m_read_or_write ? VX_dcache_req.out_cache_driver_in_mem_write : VX_dcache_req.out_cache_driver_in_mem_read);
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//assign VX_dram_req_rsp.i_m_ready = i_m_ready && !VX_dram_req_rsp_icache.o_m_valid && VX_dram_req_rsp.o_m_valid;
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//assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready && VX_dram_req_rsp_icache.o_m_valid;
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genvar cur_bank;
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genvar cur_word;
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for (cur_bank = 0; cur_bank < CACHE_BANKS; cur_bank = cur_bank + 1) begin
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for (cur_word = 0; cur_word < NUM_WORDS_PER_BLOCK; cur_word = cur_word + 1) begin
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assign VX_L2cache_req.out_cache_driver_in_data[cur_bank][cur_word] = (VX_dram_req_rsp_icache.o_m_valid) ? VX_dram_req_rsp_icache.o_m_writedata[cur_bank][cur_word]
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: VX_dram_req_rsp.o_m_writedata[cur_bank][cur_word];
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assign VX_dram_req_rsp.i_m_readdata[cur_bank][cur_word] = VX_dram_req_rsp_L2.i_m_readdata[cur_bank][cur_word]; // fill in correct response data
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assign VX_dram_req_rsp_icache.i_m_readdata[cur_bank][cur_word] = VX_dram_req_rsp_L2.i_m_readdata[cur_bank][cur_word]; // fill in correct response data
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end
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end
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*/
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assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid;
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assign o_m_valid_d = VX_dram_req_rsp.o_m_valid;
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assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr;
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assign o_m_read_addr_d = VX_dram_req_rsp.o_m_read_addr;
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assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr;
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assign o_m_evict_addr_d = VX_dram_req_rsp.o_m_evict_addr;
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assign o_m_read_or_write_i = VX_dram_req_rsp_icache.o_m_read_or_write;
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assign o_m_read_or_write_d = VX_dram_req_rsp.o_m_read_or_write;
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assign VX_dram_req_rsp.i_m_ready = i_m_ready_d;
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assign VX_dram_req_rsp_icache.i_m_ready = i_m_ready_i;
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genvar curr_bank;
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genvar curr_word;
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/*
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for (curr_bank = 0; curr_bank < CACHE_BANKS; curr_bank = curr_bank + 1) begin
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for (curr_word = 0; curr_word < NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
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assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word];
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assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
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assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed
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assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed
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end
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end
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*/
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genvar curr_bank;
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genvar curr_word;
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for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin
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for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
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assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
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assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
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assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
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assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed
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end
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end
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// Icache Interface
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VX_icache_response_inter icache_response_fe();
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VX_icache_request_inter icache_request_fe();
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for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin
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for (curr_word = 0; curr_word < `ICACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
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assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word];
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assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed
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end
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end
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assign icache_response_fe.instruction = icache_response_instruction;
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assign icache_request_pc_address = icache_request_fe.pc_address;
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/////////////////////////////////////////////////////////////////////////
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@@ -137,11 +200,14 @@ VX_back_end vx_back_end(
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VX_dmem_controller VX_dmem_controller(
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.clk (clk),
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.reset (reset),
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.VX_dram_req_rsp(VX_dram_req_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_dcache_rsp (VX_dcache_rsp)
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.clk (clk),
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.reset (reset),
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.VX_dram_req_rsp (VX_dram_req_rsp),
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.VX_dram_req_rsp_icache (VX_dram_req_rsp_icache),
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.VX_icache_req (icache_request_fe),
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.VX_icache_rsp (icache_response_fe),
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.VX_dcache_req (VX_dcache_req),
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.VX_dcache_rsp (VX_dcache_rsp)
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);
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// VX_csr_handler vx_csr_handler(
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// .clk (clk),
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