snooping response handling fix

driver/rtlsim/Makefile

@@ -5,7 +5,7 @@ CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime
 
 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2
 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
-#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
+MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
 
 DEBUG = 1
 

driver/tests/basic/common.h

@@ -3,6 +3,6 @@
 
 #define DEV_MEM_SRC_ADDR 0x10000000
 #define DEV_MEM_DST_ADDR 0x20000000
-#define NUM_BLOCKS       1
+#define NUM_BLOCKS       4
 
 #endif

hw/rtl/cache/VX_cache_miss_resrv.v

@@ -31,11 +31,7 @@ module VX_cache_miss_resrv #(
 
     // Broadcast Fill
     input wire                          is_fill_st1,
-
-`IGNORE_WARNINGS_BEGIN
-    // TODO: should fix this
     input wire[`LINE_ADDR_WIDTH-1:0]    fill_addr_st1,
-`IGNORE_WARNINGS_END
 
     // Miss dequeue
     input  wire                         miss_resrv_pop,
@@ -99,6 +95,7 @@ module VX_cache_miss_resrv #(
                 tail_ptr                      <= tail_ptr + 1;
             end
 
+            // update entry as 'ready' during DRAM fill response
             if (update_ready) begin                
                 ready_table <= ready_table | make_ready;
             end

hw/rtl/cache/VX_snp_forwarder.v

@@ -47,7 +47,6 @@ module VX_snp_forwarder #(
     wire fwdin_ready;
     wire fwdin_taken;
     
-    
     assign fwdout_ready = (& snp_fwdout_ready);
 
     assign snp_req_ready = (pending_size != `LOG2UP(SNRQ_SIZE)'(SNRQ_SIZE-1)) // not full
@@ -113,4 +112,19 @@ module VX_snp_forwarder #(
         assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i));
     end
 
+    /*always_comb begin
+        if (1'($time & 1) && snp_req_valid && snp_req_ready) begin
+            $display("*** %t: ", $time);
+        end
+        if (1'($time & 1) && snp_fwdout_valid && snp_fwdout_ready) begin
+            $display("*** %t: ", $time);
+        end
+        if (1'($time & 1) && fwdin_valid && fwdin_ready) begin
+            $display("*** %t: ", $time);
+        end
+        if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin
+            $display("*** %t: ", $time);
+        end
+    end*/
+
 endmodule

hw/simulate/simulator.cpp

@@ -177,6 +177,7 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
   for (;;) {
     this->step();
     if (vortex_->snp_rsp_valid) {
+      assert(outstanding_snp_reqs > 0);
       --outstanding_snp_reqs;
     }
     if (vortex_->snp_req_valid && vortex_->snp_req_ready) {