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snooping response handling fix

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This commit is contained in:
Blaise Tine
2020-05-12 18:52:24 -04:00
parent 1eda9b34d5
commit b0b38f6c24
7 changed files with 66 additions and 54 deletions
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2
driver/rtlsim/Makefile
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@@ -5,7 +5,7 @@ CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
DEBUG = 1 DEBUG = 1

2
driver/tests/basic/common.h
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@@ -3,6 +3,6 @@
#define DEV_MEM_SRC_ADDR 0x10000000 #define DEV_MEM_SRC_ADDR 0x10000000
#define DEV_MEM_DST_ADDR 0x20000000 #define DEV_MEM_DST_ADDR 0x20000000
#define NUM_BLOCKS 1 #define NUM_BLOCKS 4
#endif #endif

BIN
driver/tests/basic/kernel.bin
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6
hw/rtl/cache/VX_bank.v vendored
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@@ -168,7 +168,7 @@ module VX_bank #(
.NUM_REQUESTS (NUM_REQUESTS), .NUM_REQUESTS (NUM_REQUESTS),
.REQQ_SIZE (REQQ_SIZE), .REQQ_SIZE (REQQ_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH), .CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(CORE_TAG_ID_BITS) .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) req_queue ( ) req_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -354,10 +354,10 @@ module VX_bank #(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.stall (stall_bank_pipe), .stall (stall_bank_pipe),
.stall_bank_pipe (stall_bank_pipe), .stall_bank_pipe(stall_bank_pipe),
// Initial Read // Initial Read
.readaddr_st10 (addr_st1[0][`LINE_SELECT_BITS-1:0]), .readaddr_st10(addr_st1[0][`LINE_SELECT_BITS-1:0]),
// Actual Read/Write // Actual Read/Write
.valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]), .valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]),

5
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -31,11 +31,7 @@ module VX_cache_miss_resrv #(
// Broadcast Fill // Broadcast Fill
input wire is_fill_st1, input wire is_fill_st1,
`IGNORE_WARNINGS_BEGIN
// TODO: should fix this
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1, input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1,
`IGNORE_WARNINGS_END
// Miss dequeue // Miss dequeue
input wire miss_resrv_pop, input wire miss_resrv_pop,
@@ -99,6 +95,7 @@ module VX_cache_miss_resrv #(
tail_ptr <= tail_ptr + 1; tail_ptr <= tail_ptr + 1;
end end
// update entry as 'ready' during DRAM fill response
if (update_ready) begin if (update_ready) begin
ready_table <= ready_table | make_ready; ready_table <= ready_table | make_ready;
end end

16
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -47,7 +47,6 @@ module VX_snp_forwarder #(
wire fwdin_ready; wire fwdin_ready;
wire fwdin_taken; wire fwdin_taken;
assign fwdout_ready = (& snp_fwdout_ready); assign fwdout_ready = (& snp_fwdout_ready);
assign snp_req_ready = (pending_size != `LOG2UP(SNRQ_SIZE)'(SNRQ_SIZE-1)) // not full assign snp_req_ready = (pending_size != `LOG2UP(SNRQ_SIZE)'(SNRQ_SIZE-1)) // not full
@@ -113,4 +112,19 @@ module VX_snp_forwarder #(
assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i)); assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i));
end end
/*always_comb begin
if (1'($time & 1) && snp_req_valid && snp_req_ready) begin
$display("*** %t: ", $time);
end
if (1'($time & 1) && snp_fwdout_valid && snp_fwdout_ready) begin
$display("*** %t: ", $time);
end
if (1'($time & 1) && fwdin_valid && fwdin_ready) begin
$display("*** %t: ", $time);
end
if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin
$display("*** %t: ", $time);
end
end*/
endmodule endmodule

1
hw/simulate/simulator.cpp
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@@ -177,6 +177,7 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
for (;;) { for (;;) {
this->step(); this->step();
if (vortex_->snp_rsp_valid) { if (vortex_->snp_rsp_valid) {
assert(outstanding_snp_reqs > 0);
--outstanding_snp_reqs; --outstanding_snp_reqs;
} }
if (vortex_->snp_req_valid && vortex_->snp_req_ready) { if (vortex_->snp_req_valid && vortex_->snp_req_ready) {