diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index cfb62219..c29005ec 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -31,16 +31,12 @@ RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../ VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE) VL_FLAGS += -Wno-DECLFILENAME +VL_FLAGS += --x-initial unique # Use 64 bytes DRAM blocks CFLAGS += -DGLOBAL_BLOCK_SIZE=64 VL_FLAGS += -DGLOBAL_BLOCK_SIZE=64 -VL_FLAGS += --x-initial unique - -VL_FLAGS += -DDPRFQ_SIZE=0 -DIPRFQ_SIZE=0 -DSPRFQ_SIZE=0 -DL2PRFQ_SIZE=0 -DL3PRFQ_SIZE=0 -VL_FLAGS += -DDFILL_INVALIDAOR_SIZE=0 -DIFILL_INVALIDAOR_SIZE=0 -DSFILL_INVALIDAOR_SIZE=0 -DL2FILL_INVALIDAOR_SIZE=0 -DL3FILL_INVALIDAOR_SIZE=0 - # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #VL_FLAGS += --threads $(THREADS) diff --git a/hw/Makefile b/hw/Makefile index cc8cc4a9..7bb9e223 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -4,6 +4,7 @@ CF += -std=c++11 -fms-extensions VF += --language 1800-2009 --assert -Wall -Wpedantic VF += -Wno-DECLFILENAME +VF += --x-initial unique VF += -exe $(SRCS) $(INCLUDE) @@ -11,8 +12,9 @@ VF += -exe $(SRCS) $(INCLUDE) CF += -DGLOBAL_BLOCK_SIZE=64 VF += -DGLOBAL_BLOCK_SIZE=64 +#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 +#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate diff --git a/hw/opae/.gitignore b/hw/opae/.gitignore new file mode 100644 index 00000000..4d9809eb --- /dev/null +++ b/hw/opae/.gitignore @@ -0,0 +1,2 @@ +build_ase*/ +build_fpga*/ \ No newline at end of file diff --git a/hw/opae/Makefile b/hw/opae/Makefile index a4a7ec6b..764afbf5 100644 --- a/hw/opae/Makefile +++ b/hw/opae/Makefile @@ -2,24 +2,32 @@ ASE_BUILD_DIR=build_ase FPGA_BUILD_DIR=build_fpga -all: ase fpga +all: ase fpga fpga-1c ase: setup-ase make -C $(ASE_BUILD_DIR) -fpga: setup-fpga - cd $(FPGA_BUILD_DIR) && qsub-synth - setup-ase: $(ASE_BUILD_DIR)/Makefile -setup-fpga: $(FPGA_BUILD_DIR)/build/dcp.qpf - $(ASE_BUILD_DIR)/Makefile: afu_sim_setup -s sources.txt $(ASE_BUILD_DIR) +fpga: setup-fpga + cd $(FPGA_BUILD_DIR) && qsub-synth + +setup-fpga: $(FPGA_BUILD_DIR)/build/dcp.qpf + $(FPGA_BUILD_DIR)/build/dcp.qpf: afu_synth_setup -s sources.txt $(FPGA_BUILD_DIR) +fpga-1c: setup-fpga-1c + cd $(FPGA_BUILD_DIR)_1c && qsub-synth + +setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf + +$(FPGA_BUILD_DIR)_1c/build/dcp.qpf: + afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c + run-ase: cd $(ASE_BUILD_DIR) && make sim diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 467d4ec6..40e6bf7c 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -4,19 +4,6 @@ vortex_afu.json +define+NUM_CORES=2 -+define+DPRFQ_SIZE=0 -+define+IPRFQ_SIZE=0 -+define+SPRFQ_SIZE=0 -+define+L2PRFQ_SIZE=0 -+define+L3PRFQ_SIZE=0 - -+define+DFILL_INVALIDAOR_SIZE=0 -+define+IFILL_INVALIDAOR_SIZE=0 -+define+SFILL_INVALIDAOR_SIZE=0 -+define+L2FILL_INVALIDAOR_SIZE=0 -+define+L3FILL_INVALIDAOR_SIZE=0 - - #+define+DBG_PRINT_CORE_ICACHE #+define+DBG_PRINT_CORE_DCACHE #+define+DBG_PRINT_CACHE_BANK diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index ace27ae2..a30475c0 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -608,7 +608,7 @@ module VX_bank #( .invalidate_fill (invalidate_fill) ); - assign dram_fill_req_valid = possible_fill && !invalidate_fill; + assign dram_fill_req_valid = miss_add && !mrvq_init_ready_state_st2; assign dram_fill_req_addr = addr_st2; assign dram_fill_req_stall = (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready); diff --git a/hw/syn/quartus/.gitignore b/hw/syn/quartus/.gitignore new file mode 100644 index 00000000..977047af --- /dev/null +++ b/hw/syn/quartus/.gitignore @@ -0,0 +1,7 @@ +/cache/bin/ +/cache/qdb/ +/cache/tmp-clearbox/ + +/top/bin/ +/top/qdb/ +/top/tmp-clearbox/ \ No newline at end of file diff --git a/hw/syn/quartus/back_end/Makefile b/hw/syn/quartus/back_end/Makefile deleted file mode 100755 index 01912f55..00000000 --- a/hw/syn/quartus/back_end/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -PROJECT = VX_back_end -TOP_LEVEL_ENTITY = VX_back_end -SRC_FILE = VX_back_end.v -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/back_end/project.sdc b/hw/syn/quartus/back_end/project.sdc deleted file mode 100755 index 16582e56..00000000 --- a/hw/syn/quartus/back_end/project.sdc +++ /dev/null @@ -1 +0,0 @@ -create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/hw/syn/quartus/back_end/project.tcl b/hw/syn/quartus/back_end/project.tcl deleted file mode 100644 index afe69d48..00000000 --- a/hw/syn/quartus/back_end/project.tcl +++ /dev/null @@ -1,41 +0,0 @@ -load_package flow -package require cmdline - -set options { \ - { "project.arg" "" "Project name" } \ - { "family.arg" "" "Device family name" } \ - { "device.arg" "" "Device name" } \ - { "top.arg" "" "Top level module" } \ - { "sdc.arg" "" "Timing Design Constraints file" } \ - { "src.arg" "" "Verilog source file" } \ - { "inc.arg" "." "Include path" } \ -} - -array set opts [::cmdline::getoptions quartus(args) $options] - -project_new $opts(project) -overwrite - -set_global_assignment -name FAMILY $opts(family) -set_global_assignment -name DEVICE $opts(device) -set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) -set_global_assignment -name VERILOG_FILE $opts(src) -set_global_assignment -name SEARCH_PATH $opts(inc) -set_global_assignment -name SDC_FILE $opts(sdc) -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 - -proc make_all_pins_virtual {} { - execute_module -tool map - set name_ids [get_names -filter * -node_type pin] - foreach_in_collection name_id $name_ids { - set pin_name [get_name_info -info full_path $name_id] - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON - } - export_assignments -} - -make_all_pins_virtual - -project_close \ No newline at end of file diff --git a/hw/syn/quartus/cache/Makefile b/hw/syn/quartus/cache/Makefile index 25db743c..a4c68207 100755 --- a/hw/syn/quartus/cache/Makefile +++ b/hw/syn/quartus/cache/Makefile @@ -64,7 +64,7 @@ asm.chg: $(STAMP) asm.chg program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" clean: rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/dmem_ctrl/Makefile b/hw/syn/quartus/dmem_ctrl/Makefile deleted file mode 100755 index 5f33f9be..00000000 --- a/hw/syn/quartus/dmem_ctrl/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -PROJECT = VX_dmem_ctrl -TOP_LEVEL_ENTITY = VX_dmem_ctrl -SRC_FILE = VX_dmem_ctrl.v -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/dmem_ctrl/project.sdc b/hw/syn/quartus/dmem_ctrl/project.sdc deleted file mode 100755 index 16582e56..00000000 --- a/hw/syn/quartus/dmem_ctrl/project.sdc +++ /dev/null @@ -1 +0,0 @@ -create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/hw/syn/quartus/dmem_ctrl/project.tcl b/hw/syn/quartus/dmem_ctrl/project.tcl deleted file mode 100644 index afe69d48..00000000 --- a/hw/syn/quartus/dmem_ctrl/project.tcl +++ /dev/null @@ -1,41 +0,0 @@ -load_package flow -package require cmdline - -set options { \ - { "project.arg" "" "Project name" } \ - { "family.arg" "" "Device family name" } \ - { "device.arg" "" "Device name" } \ - { "top.arg" "" "Top level module" } \ - { "sdc.arg" "" "Timing Design Constraints file" } \ - { "src.arg" "" "Verilog source file" } \ - { "inc.arg" "." "Include path" } \ -} - -array set opts [::cmdline::getoptions quartus(args) $options] - -project_new $opts(project) -overwrite - -set_global_assignment -name FAMILY $opts(family) -set_global_assignment -name DEVICE $opts(device) -set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) -set_global_assignment -name VERILOG_FILE $opts(src) -set_global_assignment -name SEARCH_PATH $opts(inc) -set_global_assignment -name SDC_FILE $opts(sdc) -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 - -proc make_all_pins_virtual {} { - execute_module -tool map - set name_ids [get_names -filter * -node_type pin] - foreach_in_collection name_id $name_ids { - set pin_name [get_name_info -info full_path $name_id] - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON - } - export_assignments -} - -make_all_pins_virtual - -project_close \ No newline at end of file diff --git a/hw/syn/quartus/front_end/Makefile b/hw/syn/quartus/front_end/Makefile deleted file mode 100755 index 3486c61b..00000000 --- a/hw/syn/quartus/front_end/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -PROJECT = VX_front_end -TOP_LEVEL_ENTITY = VX_front_end -SRC_FILE = VX_front_end.v -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N3F40E2SG - -# Executable Configuration -SYN_ARGS = --parallel --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --do_report_timing - -# Build targets -all: $(PROJECT).sta.rpt - -syn: $(PROJECT).syn.rpt - -fit: $(PROJECT).fit.rpt - -asm: $(PROJECT).asm.rpt - -sta: $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) - quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt - quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt - quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt - quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" - -clean: - rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/front_end/project.sdc b/hw/syn/quartus/front_end/project.sdc deleted file mode 100755 index 16582e56..00000000 --- a/hw/syn/quartus/front_end/project.sdc +++ /dev/null @@ -1 +0,0 @@ -create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/hw/syn/quartus/front_end/project.tcl b/hw/syn/quartus/front_end/project.tcl deleted file mode 100644 index afe69d48..00000000 --- a/hw/syn/quartus/front_end/project.tcl +++ /dev/null @@ -1,41 +0,0 @@ -load_package flow -package require cmdline - -set options { \ - { "project.arg" "" "Project name" } \ - { "family.arg" "" "Device family name" } \ - { "device.arg" "" "Device name" } \ - { "top.arg" "" "Top level module" } \ - { "sdc.arg" "" "Timing Design Constraints file" } \ - { "src.arg" "" "Verilog source file" } \ - { "inc.arg" "." "Include path" } \ -} - -array set opts [::cmdline::getoptions quartus(args) $options] - -project_new $opts(project) -overwrite - -set_global_assignment -name FAMILY $opts(family) -set_global_assignment -name DEVICE $opts(device) -set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) -set_global_assignment -name VERILOG_FILE $opts(src) -set_global_assignment -name SEARCH_PATH $opts(inc) -set_global_assignment -name SDC_FILE $opts(sdc) -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 - -proc make_all_pins_virtual {} { - execute_module -tool map - set name_ids [get_names -filter * -node_type pin] - foreach_in_collection name_id $name_ids { - set pin_name [get_name_info -info full_path $name_id] - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON - } - export_assignments -} - -make_all_pins_virtual - -project_close \ No newline at end of file diff --git a/hw/syn/quartus/scheduler/Makefile b/hw/syn/quartus/scheduler/Makefile index 0f2c11a3..4cad1c26 100755 --- a/hw/syn/quartus/scheduler/Makefile +++ b/hw/syn/quartus/scheduler/Makefile @@ -64,7 +64,7 @@ asm.chg: $(STAMP) asm.chg program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" clean: rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index 30fc833c..370d7320 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -64,7 +64,7 @@ asm.chg: $(STAMP) asm.chg program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" + quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" clean: rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox