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minor update

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This commit is contained in:
Blaise Tine
2020-08-31 06:17:49 -07:00
parent 0a0b28aac0
commit af84e01856
21 changed files with 870 additions and 889 deletions
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42
hw/rtl/VX_ibuffer.v
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@@ -11,6 +11,7 @@ module VX_ibuffer #(
VX_decode_if ibuf_enq_if,
// outputs
output wire [`NW_BITS-1:0] deq_wid_next,
VX_decode_if ibuf_deq_if
);
localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + 1 + `NUM_REGS;
@@ -84,12 +85,10 @@ module VX_ibuffer #(
reg deq_valid, deq_valid_n;
reg [DATAW-1:0] deq_instr, deq_instr_n;
reg [DATAW-1:0] q_data_prev_r, q_data_out_r;
always @(*) begin
valid_table_n = valid_table;
if (deq_fire) begin
valid_table_n[ibuf_deq_if.wid] = (q_size[deq_wid] != SIZEW'(1));
valid_table_n[deq_wid] = (q_size[deq_wid] != SIZEW'(1));
end
if (enq_fire) begin
valid_table_n[ibuf_enq_if.wid] = 1;
@@ -99,26 +98,26 @@ module VX_ibuffer #(
// schedule the next instruction to issue
// does round-robin scheduling when multiple warps are present
always @(*) begin
deq_valid_n = 0;
deq_wid_n = 'x;
deq_instr_n = 'x;
deq_valid_n = 0;
deq_wid_n = 'x;
deq_instr_n = 'x;
schedule_table_n = schedule_table;
if (0 == num_warps) begin
deq_valid_n = enq_fire;
deq_wid_n = ibuf_enq_if.wid;
deq_instr_n = q_data_in;
deq_valid_n = enq_fire;
deq_wid_n = ibuf_enq_if.wid;
deq_instr_n = q_data_in;
end else if ((1 == num_warps) || freeze) begin
deq_valid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) || enq_fire;
deq_wid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) ? deq_wid : ibuf_enq_if.wid;
deq_instr_n = deq_fire ? ((q_size[deq_wid] != SIZEW'(1)) ? q_data_prev_r : q_data_in) : q_data_out_r;
deq_valid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) || enq_fire;
deq_wid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) ? deq_wid : ibuf_enq_if.wid;
deq_instr_n = deq_fire ? ((q_size[deq_wid] != SIZEW'(1)) ? q_data_prev[deq_wid] : q_data_in) : q_data_out[deq_wid];
end else begin
for (integer i = 0; i < `NUM_WARPS; i++) begin
if (schedule_table_n[i]) begin
deq_valid_n = 1;
deq_wid_n = `NW_BITS'(i);
deq_instr_n = q_data_out[i];
deq_valid_n = 1;
deq_wid_n = `NW_BITS'(i);
deq_instr_n = q_data_out[i];
schedule_table_n[i] = 0;
break;
end
@@ -127,7 +126,7 @@ module VX_ibuffer #(
end
wire warp_added = enq_fire && (0 == q_size[ibuf_enq_if.wid]);
wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == ibuf_deq_if.wid) && (1 == q_size[ibuf_deq_if.wid]);
wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == deq_wid) && ~(q_size[deq_wid] != SIZEW'(1));
always @(posedge clk) begin
if (reset) begin
@@ -145,12 +144,9 @@ module VX_ibuffer #(
schedule_table[deq_wid_n] <= 0;
end
q_data_out_r <= (0 == num_warps) ? q_data_in : q_data_out[deq_wid_n];
q_data_prev_r <= q_data_prev[deq_wid_n];
deq_valid <= deq_valid_n;
deq_wid <= deq_wid_n;
deq_instr <= deq_instr_n;
deq_valid <= deq_valid_n;
deq_wid <= deq_wid_n;
deq_instr <= deq_instr_n;
if (warp_added && !warp_removed) begin
num_warps <= num_warps + NWARPSW'(1);
@@ -176,6 +172,8 @@ module VX_ibuffer #(
end
end
assign deq_wid_next = deq_wid_n;
assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid];
assign q_data_in = {ibuf_enq_if.thread_mask,
ibuf_enq_if.curr_PC,