wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!

Browse Source
This commit is contained in:
Blaise Tine
2020-11-05 03:49:50 -08:00
parent 4c6a74fa87
commit af2bb3b789
8 changed files with 334 additions and 212 deletions
Download Patch File Download Diff File Expand all files Collapse all files

275
hw/rtl/libs/VX_dp_ram.v
View File

@@ -8,7 +8,8 @@ module VX_dp_ram #(
parameter RWCHECK = 1,
parameter RWBYPASS = 0,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1)
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
@@ -20,67 +21,12 @@ module VX_dp_ram #(
output wire [DATAW-1:0] dout
);
if (BUFFERED) begin
if (FASTRAM) begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] dout_r;
if (BUFFERED) begin
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
if (RWBYPASS) begin
reg [DATAW-1:0] din_r;
wire writing;
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
din_r <= din;
end
end
reg bypass_r;
always @(posedge clk) begin
bypass_r <= wren && (raddr == waddr);
end
assign dout = bypass_r ? din_r : dout_r;
end else begin
assign dout = dout_r;
end
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
always @(posedge clk) begin
@@ -97,12 +43,17 @@ module VX_dp_ram #(
mem[waddr] <= din;
end
end
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
if (RWBYPASS) begin
reg [DATAW-1:0] din_r;
wire writing;
if (BYTEENW > 1) begin
reg [DATAW-1:0] din_r;
wire writing;
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
@@ -118,17 +69,95 @@ module VX_dp_ram #(
reg bypass_r;
always @(posedge clk) begin
bypass_r <= writing && (raddr == waddr);
bypass_r <= wren && (raddr == waddr);
end
assign dout = bypass_r ? din_r : mem[raddr];
assign dout = bypass_r ? din_r : dout_r;
end else begin
assign dout = mem[raddr];
assign dout = dout_r;
end
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
if (RWBYPASS) begin
reg [DATAW-1:0] din_r;
wire writing;
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
din_r <= din;
end
end
reg bypass_r;
always @(posedge clk) begin
bypass_r <= writing && (raddr == waddr);
end
assign dout = bypass_r ? din_r : mem[raddr];
end else begin
assign dout = mem[raddr];
end
end else begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
end
end
end else begin
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BUFFERED) begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
always @(posedge clk) begin
@@ -145,7 +174,113 @@ module VX_dp_ram #(
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
if (RWBYPASS) begin
reg [DATAW-1:0] din_r;
wire writing;
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
din_r <= din;
end
end
reg bypass_r;
always @(posedge clk) begin
bypass_r <= wren && (raddr == waddr);
end
assign dout = bypass_r ? din_r : dout_r;
end else begin
assign dout = dout_r;
end
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
if (RWBYPASS) begin
reg [DATAW-1:0] din_r;
wire writing;
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
din_r[i * 8 +: 8] <= byteen[i] ? din[i * 8 +: 8] : mem[waddr][i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
din_r <= din;
end
end
reg bypass_r;
always @(posedge clk) begin
bypass_r <= writing && (raddr == waddr);
end
assign dout = bypass_r ? din_r : mem[raddr];
end else begin
assign dout = mem[raddr];
end
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
end
end
end
end else begin
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
end
end
end

9
hw/rtl/libs/VX_generic_queue.v
View File

@@ -5,7 +5,8 @@ module VX_generic_queue #(
parameter SIZE = 2,
parameter BUFFERED = 0,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1)
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 1
) (
input wire clk,
input wire reset,
@@ -108,7 +109,8 @@ module VX_generic_queue #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(0),
.RWCHECK(1)
.RWCHECK(1),
.FASTRAM(FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_a),
@@ -161,7 +163,8 @@ module VX_generic_queue #(
.DATAW(DATAW),
.SIZE(SIZE),
.BUFFERED(1),
.RWCHECK(0)
.RWCHECK(0),
.FASTRAM(FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),