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sp_ram byteen fix

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Blaise Tine
2021-01-15 16:28:03 -08:00
parent 7ae936c25f
commit ad6e0b4e77
2 changed files with 21 additions and 33 deletions
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1
hw/opae/README
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@@ -96,6 +96,7 @@ gtkwave ./build_ase_1c/work/vortex.vcd &
# kill process by Users # kill process by Users
ps -u tinebp ps -u tinebp
kill -9 <pid> kill -9 <pid>
ps -u tinebp | grep "blackbox" | awk '{print $1}' | xargs kill -9
# fixing device resource busy issue when deleting /build_ase_1c/ # fixing device resource busy issue when deleting /build_ase_1c/
lsof +D build_ase_1c lsof +D build_ase_1c

53
hw/rtl/libs/VX_sp_ram.v
View File

@@ -22,23 +22,18 @@ module VX_sp_ram #(
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
localparam DATA32W = DATAW / 32;
localparam BYTEEN32W = BYTEENW / 4;
if (FASTRAM) begin if (FASTRAM) begin
if (BUFFERED) begin if (BUFFERED) begin
reg [DATAW-1:0] dout_r; reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (wren) begin if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin for (integer i = 0; i < BYTEENW; i++) begin
for (integer i = 0; i < 4; i++) begin if (byteen[i])
if (byteen[j * 4 + i]) mem[addr][i] <= din[i * 8 +: 8];
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end end
end end
if (rden) if (rden)
@@ -58,15 +53,13 @@ module VX_sp_ram #(
end else begin end else begin
`UNUSED_VAR (rden) `UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (wren) begin if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin for (integer i = 0; i < BYTEENW; i++) begin
for (integer i = 0; i < 4; i++) begin if (byteen[i])
if (byteen[j * 4 + i]) mem[addr][i] <= din[i * 8 +: 8];
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end end
end end
end end
@@ -86,15 +79,13 @@ module VX_sp_ram #(
reg [DATAW-1:0] dout_r; reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (wren) begin if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin for (integer i = 0; i < BYTEENW; i++) begin
for (integer i = 0; i < 4; i++) begin if (byteen[i])
if (byteen[j * 4 + i]) mem[addr][i] <= din[i * 8 +: 8];
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end end
end end
if (rden) if (rden)
@@ -115,15 +106,13 @@ module VX_sp_ram #(
`UNUSED_VAR (rden) `UNUSED_VAR (rden)
if (RWCHECK) begin if (RWCHECK) begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (wren) begin if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin for (integer i = 0; i < BYTEENW; i++) begin
for (integer i = 0; i < 4; i++) begin if (byteen[i])
if (byteen[j * 4 + i]) mem[addr][i] <= din[i * 8 +: 8];
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end end
end end
end end
@@ -139,15 +128,13 @@ module VX_sp_ram #(
end end
end else begin end else begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (wren) begin if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin for (integer i = 0; i < BYTEENW; i++) begin
for (integer i = 0; i < 4; i++) begin if (byteen[i])
if (byteen[j * 4 + i]) mem[addr][i] <= din[i * 8 +: 8];
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end end
end end
end end