wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

tabs cleanup

Browse Source
This commit is contained in:
Blaise Tine
2020-11-28 17:08:01 -05:00
parent 00d7473268
commit ac1883a13f
21 changed files with 275 additions and 275 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
hw/rtl/libs/VX_dp_ram.v
View File

@@ -11,14 +11,14 @@ module VX_dp_ram #(
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire wren,
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
input wire rden,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
);
if (FASTRAM) begin