cache optimization - moved read requests to stage1 and eliminating stage3
This commit is contained in:
Blaise Tine
94
hw/rtl/cache/VX_miss_resrv.v
vendored
94
hw/rtl/cache/VX_miss_resrv.v
vendored
@@ -24,36 +24,34 @@ module VX_miss_resrv #(
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc_st0,
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input wire[`NR_BITS-1:0] debug_rd_st0,
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input wire[`NW_BITS-1:0] debug_wid_st0,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0,
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input wire[31:0] debug_pc_st3,
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input wire[`NR_BITS-1:0] debug_rd_st3,
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input wire[`NW_BITS-1:0] debug_wid_st3,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st3,
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input wire[31:0] deq_debug_pc,
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input wire[`NW_BITS-1:0] deq_debug_wid,
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input wire[31:0] enq_debug_pc,
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input wire[`NW_BITS-1:0] enq_debug_wid,
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`IGNORE_WARNINGS_END
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`endif
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// enqueue
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input wire enqueue_st3,
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input wire [`LINE_ADDR_WIDTH-1:0] enqueue_addr_st3,
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input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data_st3,
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input wire enqueue_is_mshr_st3,
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input wire enqueue_ready_st3,
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input wire enqueue,
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input wire [`LINE_ADDR_WIDTH-1:0] enqueue_addr,
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input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data,
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input wire enqueue_is_mshr,
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input wire enqueue_ready,
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output wire enqueue_full,
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// fill
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input wire update_ready_st0,
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input wire [`LINE_ADDR_WIDTH-1:0] addr_st0,
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output wire pending_hazard_st0,
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// lookup
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input wire lookup_ready,
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input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr,
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output wire lookup_match,
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// schedule
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input wire schedule,
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output wire schedule_valid,
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output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr,
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output wire [`MSHR_DATA_WIDTH-1:0] schedule_data,
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// dequeue
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input wire schedule_st0,
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output wire dequeue_valid_st0,
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output wire [`LINE_ADDR_WIDTH-1:0] dequeue_addr_st0,
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output wire [`MSHR_DATA_WIDTH-1:0] dequeue_data_st0,
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input wire dequeue_st3
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input wire dequeue
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);
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`USE_FAST_BRAM reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
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@@ -67,17 +65,17 @@ module VX_miss_resrv #(
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wire [MSHR_SIZE-1:0] valid_address_match;
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for (genvar i = 0; i < MSHR_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] == addr_st0);
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] == lookup_addr);
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end
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assign pending_hazard_st0 = (| valid_address_match);
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assign lookup_match = (| valid_address_match);
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wire dequeue_ready = ready_table[schedule_ptr];
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assign dequeue_valid_st0 = dequeue_ready;
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assign dequeue_addr_st0 = addr_table[schedule_ptr];
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assign schedule_valid = dequeue_ready;
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assign schedule_addr = addr_table[schedule_ptr];
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wire mshr_push = enqueue_st3 && !enqueue_is_mshr_st3;
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wire mshr_push = enqueue && !enqueue_is_mshr;
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wire [`LOG2UP(MSHR_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
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@@ -91,33 +89,33 @@ module VX_miss_resrv #(
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tail_ptr <= 0;
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size <= 0;
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end else begin
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if (update_ready_st0) begin
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if (lookup_ready) begin
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ready_table <= ready_table | valid_address_match;
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end
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if (enqueue_st3) begin
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if (enqueue) begin
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assert(!enqueue_full);
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if (enqueue_is_mshr_st3) begin
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if (enqueue_is_mshr) begin
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// returning missed msrq entry, restore schedule
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valid_table[restore_ptr] <= 1;
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ready_table[restore_ptr] <= enqueue_ready_st3;
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ready_table[restore_ptr] <= enqueue_ready;
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restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
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schedule_ptr <= head_ptr;
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end else begin
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valid_table[tail_ptr] <= 1;
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ready_table[tail_ptr] <= enqueue_ready_st3;
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ready_table[tail_ptr] <= enqueue_ready;
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tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
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size <= size + $bits(size)'(1);
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end
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end else if (dequeue_st3) begin
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end else if (dequeue) begin
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head_ptr <= head_ptr_n;
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restore_ptr <= head_ptr_n;
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valid_table[head_ptr] <= 0;
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size <= size - $bits(size)'(1);
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end
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if (schedule_st0) begin
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assert(dequeue_valid_st0);
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if (schedule) begin
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assert(schedule_valid);
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valid_table[schedule_ptr] <= 0;
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ready_table[schedule_ptr] <= 0;
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schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
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@@ -126,8 +124,8 @@ module VX_miss_resrv #(
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end
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always @(posedge clk) begin
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if (enqueue_st3 && !enqueue_is_mshr_st3) begin
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addr_table[tail_ptr] <= enqueue_addr_st3;
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if (enqueue && !enqueue_is_mshr) begin
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addr_table[tail_ptr] <= enqueue_addr;
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end
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end
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@@ -142,23 +140,23 @@ module VX_miss_resrv #(
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.wren(mshr_push),
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.byteen(1'b1),
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.rden(1'b1),
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.din(enqueue_data_st3),
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.dout(dequeue_data_st0)
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.din(enqueue_data),
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.dout(schedule_data)
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);
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`ifdef DBG_PRINT_CACHE_MSHR
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always @(posedge clk) begin
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if (update_ready_st0 || schedule_st0 || enqueue_st3 || dequeue_st3) begin
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if (schedule_st0)
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$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(dequeue_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);
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if (enqueue_st3) begin
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if (enqueue_is_mshr_st3)
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$display("%t: cache%0d:%0d msrq-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3);
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if (lookup_ready || schedule || enqueue || dequeue) begin
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if (schedule)
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$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
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if (enqueue) begin
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if (enqueue_is_mshr)
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$display("%t: cache%0d:%0d msrq-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_ready);
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else
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$display("%t: cache%0d:%0d msrq-enq: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr_st3, BANK_ID), enqueue_ready_st3, debug_wid_st3, debug_pc_st3);
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$display("%t: cache%0d:%0d msrq-enq: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_ready, enq_debug_wid, enq_debug_pc);
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end
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if (dequeue_st3)
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$display("%t: cache%0d:%0d msrq-deq addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, debug_wid_st3, debug_pc_st3);
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if (dequeue)
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$display("%t: cache%0d:%0d msrq-deq addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc);
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$write("%t: cache%0d:%0d msrq-table", $time, CACHE_ID, BANK_ID);
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for (integer j = 0; j < MSHR_SIZE; j++) begin
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if (valid_table[j]) begin
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