cache optimization - moved read requests to stage1 and eliminating stage3
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2
hw/rtl/cache/VX_data_store.v
vendored
2
hw/rtl/cache/VX_data_store.v
vendored
@@ -18,7 +18,7 @@ module VX_data_store #(
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input wire write_enable,
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input wire write_fill,
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input wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable,
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input wire[BANK_LINE_SIZE-1:0] byte_enable,
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input wire[`LINE_SELECT_BITS-1:0] write_addr,
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input wire[`BANK_LINE_WIDTH-1:0] write_data,
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