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cache request interfaces update

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This commit is contained in:
Blaise Tine
2021-02-10 20:55:04 -08:00
parent 665b97b810
commit ab63ac9e5d
19 changed files with 275 additions and 192 deletions
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10
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -69,7 +69,7 @@ module VX_shared_mem #(
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_unqual;
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_unqual;
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual;
wire [NUM_BANKS-1:0] per_bank_core_req_ready_unqual;
wire per_bank_core_req_ready_unqual;
VX_cache_core_req_bank_sel #(
.CACHE_LINE_SIZE (WORD_SIZE),
@@ -78,7 +78,8 @@ module VX_shared_mem #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET)
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET),
.SHARED_BANK_READY(1)
) core_req_bank_sel (
.clk (clk),
.reset (reset),
@@ -103,9 +104,6 @@ module VX_shared_mem #(
.per_bank_core_req_ready (per_bank_core_req_ready_unqual)
);
`UNUSED_VAR (per_bank_core_req_tag_unqual)
`UNUSED_VAR (per_bank_core_req_rw_unqual)
wire [NUM_BANKS-1:0] per_bank_core_req_valid;
wire [NUM_BANKS-1:0] per_bank_core_req_rw;
wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr;
@@ -120,7 +118,7 @@ module VX_shared_mem #(
assign creq_push = (| core_req_valid) && !creq_full;
assign creq_pop = ~creq_empty && ~crsq_full;
assign per_bank_core_req_ready_unqual = {NUM_BANKS{~creq_full}};
assign per_bank_core_req_ready_unqual = ~creq_full;
wire [NUM_REQS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr_qual;
`UNUSED_VAR (per_bank_core_req_addr_unqual)