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New Cache Design Passing All Tests

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This commit is contained in:
felsabbagh3
2020-03-04 23:24:32 -08:00
parent aa1a0ee376
commit a86a403ca9
12 changed files with 194 additions and 103 deletions
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7
rtl/VX_front_end.v
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@@ -37,6 +37,9 @@ wire icache_stage_delay;
wire vortex_ebreak;
wire terminate_sim;
wire[`NW_M1:0] icache_stage_wid;
wire[`NT-1:0] icache_stage_valids;
assign fetch_ebreak = vortex_ebreak || terminate_sim;
@@ -46,6 +49,8 @@ VX_join_inter VX_join();
VX_fetch vx_fetch(
.clk (clk),
.reset (reset),
.icache_stage_wid (icache_stage_wid),
.icache_stage_valids(icache_stage_valids),
.VX_wstall (VX_wstall),
.VX_join (VX_join),
.schedule_delay (schedule_delay),
@@ -74,6 +79,8 @@ VX_icache_stage VX_icache_stage(
.clk (clk),
.reset (reset),
.icache_stage_delay(icache_stage_delay),
.icache_stage_valids(icache_stage_valids),
.icache_stage_wid (icache_stage_wid),
.fe_inst_meta_fi (fe_inst_meta_fi2),
.fe_inst_meta_id (fe_inst_meta_id),
.icache_response (icache_response_fe),