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New Cache Design Passing All Tests

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This commit is contained in:
felsabbagh3
2020-03-04 23:24:32 -08:00
parent aa1a0ee376
commit a86a403ca9
12 changed files with 194 additions and 103 deletions
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8
rtl/VX_cache/VX_cache_config.v
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@@ -39,7 +39,7 @@
`define DFQQ_SIZE `REQQ_SIZE
// Dram knobs
`define SIMULATED_DRAM_LATENCY_CYCLES 50
`define SIMULATED_DRAM_LATENCY_CYCLES 10
// ========================================= Configurable Knobs =========================================
@@ -89,8 +89,8 @@
`define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS
`define BANK_LINE_COUNT `BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES
`define BANK_LINE_SIZE_WORDS `BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES
`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES)
`define BANK_LINE_SIZE_WORDS (`BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES)
`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
// Offset is fixed
@@ -106,7 +106,7 @@
`define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END
`define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END
`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:`WORD_SELECT_SIZE_END
`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0
`define BANK_SELECT_NUM_BITS $clog2(`NUMBER_BANKS)
`define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS