set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

2020-06-29 08:03:19 -07:00
parent d33916f1e0
commit a70562d386
8 changed files with 40 additions and 11 deletions
--- a/hw/syn/quartus/project.sdc
+++ b/hw/syn/quartus/project.sdc
@@ -1,6 +1,6 @@
 set_time_format -unit ns -decimal_places 3

-create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
+create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

 derive_pll_clocks -create_base_clocks
 derive_clock_uncertainty