diff --git a/rtl/Makefile b/rtl/Makefile
index 5fb2eb5b..b0dcdf6f 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -3,9 +3,11 @@ all: RUNFILE
 
 INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
 
-FILE=Vortex.v
+SINGLE_CORE=Vortex.v
+MULTI_CORE=Vortex_SOC.v
 
 EXE=--exe ./simulate/test_bench.cpp
+MULTI_EXE=--exe ./simulate/multi_test_bench.cpp
 
 COMP=--compiler gcc
 
@@ -24,18 +26,24 @@ DEB=--trace --prof-cfuncs -DVL_DEBUG=1
 
 MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
 
+MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
+
 # -LDFLAGS '-lsystemc'
 VERILATOR:
 	echo "#define VCD_OFF" > simulate/tb_debug.h
-	verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
+	verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
 
 VERILATORnoWarnings:
 	echo "#define VCD_OFF" > simulate/tb_debug.h
-	verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF)  $(WNO) $(DEB)
+	verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF)  $(WNO) $(DEB)
+
+VERILATORMULTInoWarnings:
+	echo "#define VCD_OFF" > simulate/tb_debug.h
+	verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) $(CF)  $(WNO) $(DEB)
 
 compdebug:
 	echo "#define VCD_OUTPUT" > simulate/tb_debug.h
-	verilator_bin_dbg $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO)  $(DEB)
+	verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO)  $(DEB)
 
 RUNFILE: VERILATOR
 	$(MAKECPP)
@@ -46,6 +54,9 @@ debug: compdebug
 w: VERILATORnoWarnings
 	$(MAKECPP)
 
+multicore: VERILATORMULTInoWarnings
+	$(MAKEMULTICPP)
+
 run: w
 	(cd obj_dir && ./VVortex)
 
diff --git a/rtl/Vortex_SOC.v b/rtl/Vortex_SOC.v
new file mode 100644
index 00000000..56f50f36
--- /dev/null
+++ b/rtl/Vortex_SOC.v
@@ -0,0 +1,88 @@
+`include "VX_define.v"
+`include "VX_cache_config.v"
+
+module Vortex_SOC (
+    input  wire           clk,
+    input  wire           reset,
+    input  wire[31:0] icache_response_instruction,
+    output wire[31:0] icache_request_pc_address,
+    // IO
+    output wire        io_valid,
+    output wire[31:0]  io_data,
+
+    // DRAM Dcache Req
+    output wire                              dram_req,
+    output wire                              dram_req_write,
+    output wire                              dram_req_read,
+    output wire [31:0]                       dram_req_addr,
+    output wire [31:0]                       dram_req_size,
+    output wire [31:0]                       dram_req_data[`DBANK_LINE_SIZE_RNG],
+    output wire [31:0]                       dram_expected_lat,
+
+    // DRAM Dcache Res
+    output wire                              dram_fill_accept,
+    input  wire                              dram_fill_rsp,
+    input  wire [31:0]                       dram_fill_rsp_addr,
+    input  wire [31:0]                       dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
+
+
+    // DRAM Icache Req
+    output wire                              I_dram_req,
+    output wire                              I_dram_req_write,
+    output wire                              I_dram_req_read,
+    output wire [31:0]                       I_dram_req_addr,
+    output wire [31:0]                       I_dram_req_size,
+    output wire [31:0]                       I_dram_req_data[`DBANK_LINE_SIZE_RNG],
+    output wire [31:0]                       I_dram_expected_lat,
+
+    // DRAM Icache Res
+    output wire                              I_dram_fill_accept,
+    input  wire                              I_dram_fill_rsp,
+    input  wire [31:0]                       I_dram_fill_rsp_addr,
+    input  wire [31:0]                       I_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
+
+
+    output wire        out_ebreak
+	);
+
+
+    Vortex vortex_core(
+        .clk                        (clk),
+        .reset                      (reset),
+        .icache_response_instruction(icache_response_instruction),
+        .icache_request_pc_address  (icache_request_pc_address),
+        .io_valid                   (io_valid),
+        .io_data                    (io_data),
+        .dram_req                   (dram_req),
+        .dram_req_write             (dram_req_write),
+        .dram_req_read              (dram_req_read),
+        .dram_req_addr              (dram_req_addr),
+        .dram_req_size              (dram_req_size),
+        .dram_req_data              (dram_req_data),
+        .dram_expected_lat          (dram_expected_lat),
+        .dram_fill_accept           (dram_fill_accept),
+        .dram_fill_rsp              (dram_fill_rsp),
+        .dram_fill_rsp_addr         (dram_fill_rsp_addr),
+        .dram_fill_rsp_data         (dram_fill_rsp_data),
+        .I_dram_req                 (I_dram_req),
+        .I_dram_req_write           (I_dram_req_write),
+        .I_dram_req_read            (I_dram_req_read),
+        .I_dram_req_addr            (I_dram_req_addr),
+        .I_dram_req_size            (I_dram_req_size),
+        .I_dram_req_data            (I_dram_req_data),
+        .I_dram_expected_lat        (I_dram_expected_lat),
+        .I_dram_fill_accept         (I_dram_fill_accept),
+        .I_dram_fill_rsp            (I_dram_fill_rsp),
+        .I_dram_fill_rsp_addr       (I_dram_fill_rsp_addr),
+        .I_dram_fill_rsp_data       (I_dram_fill_rsp_data),
+        .out_ebreak                 (out_ebreak)
+        );
+
+
+
+	
+
+
+	
+
+endmodule
\ No newline at end of file
diff --git a/rtl/simulate/multi_test_bench.cpp b/rtl/simulate/multi_test_bench.cpp
new file mode 100644
index 00000000..6da0928e
--- /dev/null
+++ b/rtl/simulate/multi_test_bench.cpp
@@ -0,0 +1,112 @@
+#include "multi_test_bench.h"
+
+#define NUM_TESTS 46
+
+int main(int argc, char **argv)
+{
+
+	// Verilated::debug(1);
+
+	Verilated::commandArgs(argc, argv);
+
+	Verilated::traceEverOn(true);
+
+
+// #define ALL_TESTS
+#ifdef ALL_TESTS
+     bool passed = true;
+	 std::string tests[NUM_TESTS] = {
+	 	"../../emulator/riscv_tests/rv32ui-p-add.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-addi.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-and.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-andi.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-beq.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-bge.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-blt.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-bne.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-jal.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-lw.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-lb.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-lh.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-lui.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-or.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-ori.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sb.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sh.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-simple.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sll.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-slli.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-slt.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-slti.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sra.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-srai.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-srl.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-srli.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sub.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-sw.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-xor.hex",
+	 	"../../emulator/riscv_tests/rv32ui-p-xori.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-div.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-divu.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-mul.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-mulh.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-rem.hex",
+	 	"../../emulator/riscv_tests/rv32um-p-remu.hex"
+	 };
+
+    for (std::string s : tests) {
+        Vortex v;
+
+        std::cerr << DEFAULT << "\n---------------------------------------\n";
+
+        std::cerr << s << std::endl;
+
+        bool curr = v.simulate(s);
+        if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
+        if (!curr) std::cerr << RED   << "Test Failed: " << s << std::endl;
+        std::cerr << DEFAULT;
+        passed = passed && curr;
+    }
+
+    std::cerr << DEFAULT << "\n***************************************\n";
+
+    if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
+	if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
+
+	return !passed;
+
+	#else
+
+	char testing[] = "../../runtime/mains/simple/vx_simple_main.hex";
+	// char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
+	// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
+	Vortex v;
+	// const char *testing;
+
+	// if (argc >= 2) {
+	//     testing = argv[1];
+	// } else {
+	//     testing = "../../kernel/vortex_test.hex";
+	// }
+
+    std::cerr << testing << std::endl;
+
+
+	bool curr = v.simulate(testing);
+	if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
+	if (!curr) std::cerr << RED   << "Test Failed: " << testing << std::endl;
+
+    return !curr;
+
+#endif
+}
diff --git a/rtl/simulate/multi_test_bench.h b/rtl/simulate/multi_test_bench.h
new file mode 100644
index 00000000..06850e5a
--- /dev/null
+++ b/rtl/simulate/multi_test_bench.h
@@ -0,0 +1,481 @@
+// C++ libraries
+#include <utility> 
+#include <iostream>
+#include <map> 
+#include <iterator>
+#include <iomanip>
+#include <fstream>
+#include <unistd.h>
+#include <vector>
+#include <math.h>
+#include <algorithm>
+
+#include "VX_define.h"
+#include "ram.h"
+#include "VVortex_SOC.h"
+#include "verilated.h"
+
+#include "tb_debug.h"
+
+#ifdef VCD_OUTPUT
+#include <verilated_vcd_c.h>
+#endif
+
+unsigned long time_stamp = 0;
+
+double sc_time_stamp() 
+{ 
+  return time_stamp / 1000.0; 
+}
+
+typedef struct
+{
+    int cycles_left;
+    int data_length;
+    unsigned base_addr;
+    unsigned * data;
+} dram_req_t;
+
+class Vortex
+{
+    public:
+        Vortex();
+        ~Vortex();
+        bool simulate(std::string);
+    private:
+    	void ProcessFile(void);
+        void print_stats(bool = true);
+        bool ibus_driver();
+        bool dbus_driver();
+        void io_handler();
+
+        RAM ram;
+
+        VVortex_SOC * vortex;
+
+        unsigned start_pc;
+        bool     refill_d;
+        unsigned refill_addr_d;
+        bool     refill_i;
+        unsigned refill_addr_i;
+        long int curr_cycle;
+        bool stop;
+        bool unit_test;
+        std::string instruction_file_name;
+        std::ofstream results;
+        int stats_static_inst;
+        int stats_dynamic_inst;
+        int stats_total_cycles;
+        int stats_fwd_stalls;
+        int stats_branch_stalls;
+        int debug_state;
+        int ibus_state;
+        int dbus_state;
+        int debug_return;
+        int debug_wait_num;
+        int debug_inst_num;
+        int debug_end_wait;
+        int debug_debugAddr;
+        double stats_sim_time;
+        std::vector<dram_req_t> dram_req_vec;
+        std::vector<dram_req_t> I_dram_req_vec;
+        #ifdef VCD_OUTPUT
+        VerilatedVcdC   *m_trace;
+        #endif
+};
+
+
+
+Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
+                                                    stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
+                                                    debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
+                                                    debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
+{
+	this->vortex  = new VVortex_SOC;
+    #ifdef VCD_OUTPUT
+    this->m_trace = new VerilatedVcdC;
+    this->vortex->trace(m_trace, 99);
+    this->m_trace->open("trace.vcd");
+    #endif
+    this->results.open("../results.txt");
+}
+
+Vortex::~Vortex()
+{
+    #ifdef VCD_OUTPUT
+    m_trace->close();
+    #endif
+	this->results.close();
+	delete this->vortex;
+}
+
+
+void Vortex::ProcessFile(void)
+{
+    loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
+}
+
+void Vortex::print_stats(bool cycle_test)
+{
+
+    if (cycle_test)
+    {
+        this->results << std::left;
+        // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
+        this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
+        this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
+        this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
+        this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
+        this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
+        this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
+    }
+    else
+    {
+        this->results << std::left;
+        this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
+        this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
+    }
+
+
+    uint32_t status;
+    ram.getWord(0, &status);
+
+    if (this->unit_test)
+    {
+        if (status == 1)
+        {
+            this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
+        } else
+        {
+            this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
+        }
+    }
+    else
+    {
+        this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
+    }
+
+    this->stats_static_inst   =  0;
+    this->stats_dynamic_inst  = -1;
+    this->stats_total_cycles  =  0;
+    this->stats_fwd_stalls    =  0;
+    this->stats_branch_stalls =  0;
+
+}
+
+bool Vortex::ibus_driver()
+{
+    
+    // Iterate through each element, and get pop index
+    int dequeue_index  = -1;
+    bool dequeue_valid = false;
+    for (int i = 0; i < this->I_dram_req_vec.size(); i++)
+    {
+        if (this->I_dram_req_vec[i].cycles_left > 0)
+        {
+            this->I_dram_req_vec[i].cycles_left -= 1;   
+        }
+
+        if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
+        {
+            dequeue_index = i;
+            dequeue_valid = true;
+        }
+    }
+
+
+    if (vortex->I_dram_req)
+    {
+        // std::cout << "Icache Dram Request received!\n";
+        if (vortex->I_dram_req_read)
+        {
+            // std::cout << "Icache Dram Request is read!\n";
+            // Need to add an element
+            dram_req_t dram_req;
+            dram_req.cycles_left = vortex->I_dram_expected_lat;
+            dram_req.data_length = vortex->I_dram_req_size / 4;
+            dram_req.base_addr   = vortex->I_dram_req_addr;
+            dram_req.data        = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
+
+            for (int i = 0; i < dram_req.data_length; i++)
+            {
+                unsigned curr_addr = dram_req.base_addr + (i*4);
+                unsigned data_rd;
+                ram.getWord(curr_addr, &data_rd);
+                dram_req.data[i] = data_rd;
+            }
+            // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
+            this->I_dram_req_vec.push_back(dram_req);
+        }
+
+        if (vortex->I_dram_req_write)
+        {
+            unsigned base_addr   = vortex->I_dram_req_addr;
+            unsigned data_length = vortex->I_dram_req_size / 4;
+
+            for (int i = 0; i < data_length; i++)
+            {
+                unsigned curr_addr = base_addr + (i*4);
+                unsigned data_wr   = vortex->I_dram_req_data[i];
+                ram.writeWord(curr_addr, &data_wr);
+            }
+        }
+    }
+
+    if (vortex->I_dram_fill_accept && dequeue_valid)
+    {
+        // std::cout << "Icache Dram Response Sending...!\n";
+
+        vortex->I_dram_fill_rsp      = 1;
+        vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr;
+        // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
+
+        for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++)
+        {
+            vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i];
+        }
+        free(this->I_dram_req_vec[dequeue_index].data);
+
+        this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index);
+    }
+    else
+    {
+        vortex->I_dram_fill_rsp      = 0;
+        vortex->I_dram_fill_rsp_addr = 0;
+    }
+
+    return false;
+
+}
+
+void Vortex::io_handler()
+{
+    // std::cout << "Checking\n";
+    if (vortex->io_valid)
+    {
+        uint32_t data_write = (uint32_t) vortex->io_data;
+        // std::cout << "IO VALID!\n";
+        char c = (char) data_write;
+        std::cerr << c;
+        // std::cout << c;
+
+        std::cout << std::flush;
+    }
+}
+
+
+bool Vortex::dbus_driver()
+{
+
+    // Iterate through each element, and get pop index
+    int dequeue_index  = -1;
+    bool dequeue_valid = false;
+    for (int i = 0; i < this->dram_req_vec.size(); i++)
+    {
+        if (this->dram_req_vec[i].cycles_left > 0)
+        {
+            this->dram_req_vec[i].cycles_left -= 1;   
+        }
+
+        if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
+        {
+            dequeue_index = i;
+            dequeue_valid = true;
+        }
+    }
+
+
+    if (vortex->dram_req)
+    {
+        if (vortex->dram_req_read)
+        {
+            // Need to add an element
+            dram_req_t dram_req;
+            dram_req.cycles_left = vortex->dram_expected_lat;
+            dram_req.data_length = vortex->dram_req_size / 4;
+            dram_req.base_addr   = vortex->dram_req_addr;
+            dram_req.data        = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
+
+            for (int i = 0; i < dram_req.data_length; i++)
+            {
+                unsigned curr_addr = dram_req.base_addr + (i*4);
+                unsigned data_rd;
+                ram.getWord(curr_addr, &data_rd);
+                dram_req.data[i] = data_rd;
+            }
+            // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
+            this->dram_req_vec.push_back(dram_req);
+        }
+
+        if (vortex->dram_req_write)
+        {
+            unsigned base_addr   = vortex->dram_req_addr;
+            unsigned data_length = vortex->dram_req_size / 4;
+
+            for (int i = 0; i < data_length; i++)
+            {
+                unsigned curr_addr = base_addr + (i*4);
+                unsigned data_wr   = vortex->dram_req_data[i];
+                ram.writeWord(curr_addr, &data_wr);
+            }
+        }
+    }
+
+    if (vortex->dram_fill_accept && dequeue_valid)
+    {
+        vortex->dram_fill_rsp      = 1;
+        vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
+        // std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
+
+        for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
+        {
+            vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
+        }
+        free(this->dram_req_vec[dequeue_index].data);
+
+        this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
+    }
+    else
+    {
+        vortex->dram_fill_rsp      = 0;
+        vortex->dram_fill_rsp_addr = 0;
+    }
+
+    return false;
+}
+
+
+
+bool Vortex::simulate(std::string file_to_simulate)
+{
+
+    this->instruction_file_name = file_to_simulate;
+    // this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
+
+    this->ProcessFile();
+
+    // auto start_time = std::chrono::high_resolution_clock::now();
+
+
+    static bool stop      = false;
+    static int counter    = 0;
+    counter = 0;
+    stop = false;
+
+    // auto start_time = clock();
+
+
+	// vortex->reset = 1;
+
+
+	// vortex->reset = 0;
+
+	unsigned curr_inst;
+	unsigned new_PC;
+
+	// while (this->stop && (!(stop && (counter > 5))))
+	// {
+
+	// 	// std::cout << "************* Cycle: " << cycle << "\n";
+ //        bool istop =  ibus_driver();
+ //        bool dstop = !dbus_driver();
+
+	// 	vortex->clk = 1;
+	// 	vortex->eval();
+
+
+
+	// 	vortex->clk = 0;
+	// 	vortex->eval();
+
+
+ //        stop = istop && dstop;
+
+ //        if (stop)
+ //        {
+ //            counter++;
+ //        } else
+ //        {
+ //            counter = 0;
+ //        }
+
+ //        cycle++;
+	// }
+
+    bool istop;
+    bool dstop;
+    bool cont = false;
+    // for (int i = 0; i < 500; i++)
+
+    vortex->reset = 1;
+    vortex->clk   = 0;
+    vortex->eval();
+    // m_trace->dump(10);
+    vortex->reset = 1;
+    vortex->clk   = 1;
+    vortex->eval();
+    // m_trace->dump(11);
+    vortex->reset = 0;
+    vortex->clk   = 0;
+
+    // unsigned cycles;
+    counter = 0;
+    this->stats_total_cycles = 12;
+    while (this->stop && ((counter < 5)))
+    // while (this->stats_total_cycles < 10)
+    {
+
+        // printf("-------------------------\n");
+        // std::cout << "Counter: " << counter << "\n";
+        // if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
+        // dstop = !dbus_driver();
+        #ifdef VCD_OUTPUT
+        m_trace->dump(2*this->stats_total_cycles);
+        #endif
+        vortex->clk = 1;
+        vortex->eval();
+        istop =  ibus_driver();
+        dstop = !dbus_driver();
+                  io_handler();
+
+        #ifdef VCD_OUTPUT
+        m_trace->dump((2*this->stats_total_cycles)+1);
+        #endif
+        vortex->clk = 0;
+        vortex->eval();
+        // stop = istop && dstop;
+        stop = vortex->out_ebreak;
+
+        if (stop || cont)
+        // if (istop)
+        {
+            cont = true;
+            counter++;
+        } else
+        {
+            counter = 0;
+        }
+
+        ++time_stamp;
+        ++stats_total_cycles;
+    }
+
+    std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
+
+    int status = 0;
+    // int status = (unsigned int) vortex->Vortex_SOC__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
+
+    // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
+
+    // std::cout << "Something: " <<  result << '\n';
+
+    // uint32_t status;
+    // ram.getWord(0, &status);
+
+    this->print_stats();
+
+
+
+    return (status == 1);
+    // return (1 == 1);
+}