ebreak workaround for RISC-V tests

hw/simulate/simulator.cpp

@@ -300,7 +300,7 @@ void Simulator::run() {
 
   // execute program
   while (vortex_->busy 
-      && !vortex_->ebreak) {
+      && !get_ebreak()) {
     this->step();
   }
 
@@ -308,6 +308,10 @@ void Simulator::run() {
   this->wait(5);  
 }
 
+bool Simulator::get_ebreak() const {
+  return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak;
+}
+
 int Simulator::get_last_wb_value(int reg) const {
   return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
 }

hw/simulate/simulator.h

@@ -40,7 +40,10 @@ public:
   void get_csr(int core_id, int addr, unsigned *value);
 
   void run();  
+
   int get_last_wb_value(int reg) const;  
+  
+  bool get_ebreak() const;
 
   void print_stats(std::ostream& out);
 
@@ -60,7 +63,7 @@ private:
   void eval_mem_bus();
   void eval_io_bus();
   void eval_csr_bus();
-  
+
   std::list<mem_req_t> mem_rsp_vec_;
   bool mem_rsp_active_;