code refactoring for Vivado compatibility

2021-09-29 03:24:17 -04:00
parent 18c1dc2f0e
commit a45261b530
31 changed files with 133 additions and 110 deletions
--- a/hw/rtl/interfaces/VX_fpu_to_csr_if.v
+++ b/hw/rtl/interfaces/VX_fpu_to_csr_if.v
@@ -7,7 +7,7 @@ interface VX_fpu_to_csr_if ();

    wire                 write_enable;
    wire [`NW_BITS-1:0]  write_wid;
-    fflags_t             write_fflags;
+    fpu_types::fflags_t  write_fflags;

    wire [`NW_BITS-1:0]  read_wid;
    wire [`INST_FRM_BITS-1:0] read_frm;