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code refactoring for Vivado compatibility

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This commit is contained in:
Blaise Tine
2021-09-29 03:24:17 -04:00
parent 18c1dc2f0e
commit a45261b530
31 changed files with 133 additions and 110 deletions
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2
hw/rtl/fp_cores/VX_fp_class.v
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@@ -1,5 +1,5 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
module VX_fp_class # (
parameter MAN_BITS = 23,

2
hw/rtl/fp_cores/VX_fp_cvt.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
/// Modified port of cast module from fpnew Libray
/// reference: https://github.com/pulp-platform/fpnew

6
hw/rtl/fp_cores/VX_fp_div.v
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@@ -1,8 +1,4 @@
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`include "VX_fpu_define.vh"
module VX_fp_div #(
parameter TAGW = 1,

6
hw/rtl/fp_cores/VX_fp_fma.v
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@@ -1,8 +1,4 @@
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`include "VX_fpu_define.vh"
module VX_fp_fma #(
parameter TAGW = 1,

2
hw/rtl/fp_cores/VX_fp_ncomp.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
/// Modified port of noncomp module from fpnew Libray
/// reference: https://github.com/pulp-platform/fpnew

3
hw/rtl/fp_cores/VX_fp_rounding.v
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@@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
/// Modified port of rouding module from fpnew Libray
/// reference: https://github.com/pulp-platform/fpnew

6
hw/rtl/fp_cores/VX_fp_sqrt.v
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@@ -1,8 +1,4 @@
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`include "VX_fpu_define.vh"
module VX_fp_sqrt #(
parameter TAGW = 1,

14
hw/rtl/fp_cores/VX_fpu_define.vh Normal file
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@@ -0,0 +1,14 @@
`ifndef VX_FPU_DEFINE
`define VX_FPU_DEFINE
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`IGNORE_WARNINGS_BEGIN
import fpu_types::*;
`IGNORE_WARNINGS_END
`endif

9
hw/rtl/fp_cores/VX_fpu_dpi.v
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@@ -1,7 +1,4 @@
`ifndef SYNTHESIS
`include "VX_define.vh"
`include "float_dpi.vh"
`include "VX_fpu_define.vh"
module VX_fpu_dpi #(
parameter TAGW = 1
@@ -410,6 +407,4 @@ module VX_fpu_dpi #(
assign ready_in = per_core_ready_in[core_select];
endmodule
`endif
endmodule

2
hw/rtl/fp_cores/VX_fpu_fpga.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
module VX_fpu_fpga #(
parameter TAGW = 4

2
hw/rtl/fp_cores/VX_fpu_fpnew.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
`include "fpnew_pkg.sv"
`include "defs_div_sqrt_mvp.sv"

32
hw/rtl/fp_cores/VX_fpu_types.vh Normal file
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@@ -0,0 +1,32 @@
`ifndef VX_FPU_TYPES
`define VX_FPU_TYPES
`include "VX_define.vh"
package fpu_types;
typedef struct packed {
logic is_normal;
logic is_zero;
logic is_subnormal;
logic is_inf;
logic is_nan;
logic is_quiet;
logic is_signaling;
} fp_class_t;
`define FP_CLASS_BITS $bits(fp_class_t)
typedef struct packed {
logic NV; // 4-Invalid
logic DZ; // 3-Divide by zero
logic OF; // 2-Overflow
logic UF; // 1-Underflow
logic NX; // 0-Inexact
} fflags_t;
`define FFLAGS_BITS $bits(fflags_t)
endpackage
`endif