code refactoring for Vivado compatibility

2021-09-29 03:24:17 -04:00
parent 18c1dc2f0e
commit a45261b530
31 changed files with 133 additions and 110 deletions
--- a/hw/rtl/VX_csr_data.v
+++ b/hw/rtl/VX_csr_data.v
@@ -30,6 +30,8 @@ module VX_csr_data #(
    
    input wire                      busy
 );
+    import fpu_types::*;
+    
    reg [`CSR_WIDTH-1:0] csr_satp;
    reg [`CSR_WIDTH-1:0] csr_mstatus;
    reg [`CSR_WIDTH-1:0] csr_medeleg;