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critical path optimizations

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This commit is contained in:
Blaise Tine
2021-06-23 01:51:23 -07:00
parent b8fd2308e1
commit a3a7239b4d
4 changed files with 287 additions and 60 deletions
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144
hw/rtl/libs/VX_onehot_encoder.v
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@@ -4,8 +4,10 @@
// Adapter from BaseJump STL: http://bjump.org/data_out.html
module VX_onehot_encoder #(
parameter N = 1,
parameter LN = `LOG2UP(N)
parameter N = 1,
parameter REVERSE = 0,
parameter FAST = 1,
parameter LN = `LOG2UP(N)
) (
input wire [N-1:0] data_in,
output wire [LN-1:0] data_out,
@@ -18,14 +20,24 @@ module VX_onehot_encoder #(
end else if (N == 2) begin
assign data_out = data_in[1];
assign data_out = data_in[!REVERSE];
assign valid = (| data_in);
end else begin
end else if (N == 4) begin
reg [LN-1:0] index_r;
if (N == 4) begin
if (REVERSE) begin
always @(*) begin
casez (data_in)
4'b1000: index_r = LN'(0);
4'b?100: index_r = LN'(1);
4'b??10: index_r = LN'(2);
4'b???1: index_r = LN'(3);
default: index_r = 'x;
endcase
end
end else begin
always @(*) begin
casez (data_in)
4'b0001: index_r = LN'(0);
@@ -35,7 +47,30 @@ module VX_onehot_encoder #(
default: index_r = 'x;
endcase
end
end else if (N == 8) begin
end
assign data_out = index_r;
assign valid = (| data_in);
end else if (N == 8) begin
reg [LN-1:0] index_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
8'b10000000: index_r = LN'(0);
8'b?1000000: index_r = LN'(1);
8'b??100000: index_r = LN'(2);
8'b???10000: index_r = LN'(3);
8'b????1000: index_r = LN'(4);
8'b?????100: index_r = LN'(5);
8'b??????10: index_r = LN'(6);
8'b???????1: index_r = LN'(7);
default: index_r = 'x;
endcase
end
end else begin
always @(*) begin
casez (data_in)
8'b00000001: index_r = LN'(0);
@@ -49,7 +84,38 @@ module VX_onehot_encoder #(
default: index_r = 'x;
endcase
end
end else if (N == 16) begin
end
assign data_out = index_r;
assign valid = (| data_in);
end else if (N == 16) begin
reg [LN-1:0] index_r;
if (REVERSE) begin
always @(*) begin
casez (data_in)
16'b1000000000000000: index_r = LN'(0);
16'b?100000000000000: index_r = LN'(1);
16'b??10000000000000: index_r = LN'(2);
16'b???1000000000000: index_r = LN'(3);
16'b????100000000000: index_r = LN'(4);
16'b?????10000000000: index_r = LN'(5);
16'b??????1000000000: index_r = LN'(6);
16'b???????100000000: index_r = LN'(7);
16'b????????10000000: index_r = LN'(8);
16'b?????????1000000: index_r = LN'(9);
16'b??????????100000: index_r = LN'(10);
16'b???????????10000: index_r = LN'(11);
16'b????????????1000: index_r = LN'(12);
16'b?????????????100: index_r = LN'(13);
16'b??????????????10: index_r = LN'(14);
16'b???????????????1: index_r = LN'(15);
default: index_r = 'x;
endcase
end
end else begin
always @(*) begin
casez (data_in)
16'b0000000000000001: index_r = LN'(0);
@@ -71,7 +137,66 @@ module VX_onehot_encoder #(
default: index_r = 'x;
endcase
end
end else begin
end
assign data_out = index_r;
assign valid = (| data_in);
end if (FAST) begin
`IGNORE_WARNINGS_BEGIN
localparam levels_lp = $clog2(N);
localparam aligned_width_lp = 1 << $clog2(N);
wire [levels_lp:0][aligned_width_lp-1:0] addr;
wire [levels_lp:0][aligned_width_lp-1:0] v;
// base case, also handle padding for non-power of two inputs
assign v[0] = REVERSE ? (data_in << (aligned_width_lp - N)) : ((aligned_width_lp)'(data_in));
assign addr[0] = 'x;
for (genvar level = 1; level < levels_lp+1; level=level+1) begin
localparam segments_lp = 2**(levels_lp-level);
localparam segment_slot_lp = aligned_width_lp/segments_lp;
localparam segment_width_lp = level; // how many bits are needed at each level
for (genvar segment = 0; segment < segments_lp; segment=segment+1) begin
wire [1:0] vs = {
v[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)],
v[level-1][segment*segment_slot_lp]
};
assign v[level][segment*segment_slot_lp] = (| vs);
if (level == 1) begin
assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = vs[!REVERSE];
end else begin
assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = {
vs[!REVERSE],
addr[level-1][segment*segment_slot_lp+:segment_width_lp-1] | addr[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)+:segment_width_lp-1]
};
end
end
end
assign data_out = addr[levels_lp][`LOG2UP(N)-1:0];
assign valid = v[levels_lp][0];
`IGNORE_WARNINGS_END
end else begin
reg [LN-1:0] index_r;
if (REVERSE) begin
always @(*) begin
index_r = 'x;
for (integer i = N-1; i >= 0; --i) begin
if (data_in[i]) begin
index_r = `LOG2UP(N)'(i);
end
end
end
end else begin
always @(*) begin
index_r = 'x;
for (integer i = 0; i < N; i++) begin
@@ -84,7 +209,6 @@ module VX_onehot_encoder #(
assign data_out = index_r;
assign valid = (| data_in);
end
endmodule