Using verilog For-loops + Passing all tests

2019-03-30 22:09:03 -04:00
parent 99a0792a0c
commit a3a3b21de7
17 changed files with 1204 additions and 984 deletions
--- a/rtl/VX_memory.v
+++ b/rtl/VX_memory.v
@@ -38,7 +38,7 @@ module VX_memory (

 		always @(in_mem_read, in_cache_driver_out_data) begin
 			if (in_mem_read == `LW_MEM_READ) begin
-				// $display("PC: %h ----> Received: %h", in_curr_PC, in_cache_driver_out_data);
+				$display("PC: %h ----> Received: %h for addr: ", in_curr_PC, in_cache_driver_out_data[0], in_alu_result[0]);
 			end
 		end