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Using verilog For-loops + Passing all tests

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This commit is contained in:
felsabbagh3
2019-03-30 22:09:03 -04:00
parent 99a0792a0c
commit a3a3b21de7
17 changed files with 1204 additions and 984 deletions
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46
rtl/VX_execute.v
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@@ -5,7 +5,8 @@ module VX_execute (
input wire[4:0] in_rd,
input wire[4:0] in_rs1,
input wire[4:0] in_rs2,
input wire[31:0] in_reg_data[`NT_T2_M1:0],
input wire[31:0] in_a_reg_data[`NT_M1:0],
input wire[31:0] in_b_reg_data[`NT_M1:0],
input wire[4:0] in_alu_op,
input wire[1:0] in_wb,
input wire in_rs2_src, // NEW
@@ -32,7 +33,8 @@ module VX_execute (
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_reg_data[`NT_T2_M1:0],
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output wire out_jal,
@@ -57,28 +59,46 @@ module VX_execute (
// );
// genvar index;
// genvar index_2;
// reg[5:0] index_2;
// generate
// assign index_2 = 0;
// for (index=0; index <= `NT; index=index+2)
// for (index=0; index < `NT; index=index+1)
// begin: gen_code_label
// assign index_2 = index * 2;
// VX_alu vx_alu(
// .in_reg_data (in_reg_data[index+1:index]),
// .in_reg_data (in_reg_data[(index_2+1):(index_2)]),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result[index_2])
// .out_alu_result(out_alu_result[index])
// );
// index_2 = index_2 + 1;
// end
// endgenerate
// genvar index_out_reg;
// generate
// for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
// begin
// VX_alu vx_alu_0(
// // .in_reg_data (in_reg_data[1:0]),
// .in_1 (in_a_reg_data[index_out_reg]),
// .in_2 (in_b_reg_data[index_out_reg]),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result[index_out_reg])
// );
// end
// endgenerate
VX_alu vx_alu_0(
.in_reg_data (in_reg_data[1:0]),
.in_1 (in_a_reg_data[0]),
.in_2 (in_b_reg_data[0]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
@@ -89,7 +109,8 @@ module VX_execute (
);
VX_alu vx_alu_1(
.in_reg_data (in_reg_data[3:2]),
.in_1 (in_a_reg_data[1]),
.in_2 (in_b_reg_data[1]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
@@ -99,7 +120,7 @@ module VX_execute (
.out_alu_result(out_alu_result[1])
);
assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset);
assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
assign out_jal = in_jal;
always @(*) begin
@@ -125,7 +146,8 @@ module VX_execute (
assign out_mem_read = in_mem_read;
assign out_mem_write = in_mem_write;
assign out_rs1 = in_rs1;
assign out_reg_data = in_reg_data;
assign out_a_reg_data = in_a_reg_data;
assign out_b_reg_data = in_b_reg_data;
assign out_rs2 = in_rs2;
assign out_PC_next = in_PC_next;
assign out_is_csr = in_is_csr;