Merge branch 'master' into fpga_synthesis

2020-02-18 03:35:12 -05:00
parent 61803741f8 28ce40eebf
commit a32d654263
2 changed files with 5 additions and 5 deletions
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -33,7 +33,7 @@ VERILATOR:

 VERILATORnoWarnings:
 	echo "#define VCD_OFF" > simulate/tb_debug.h
-	verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF)  $(WNO)
+	verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF)  $(WNO) $(DEB)

 compdebug:
 	echo "#define VCD_OUTPUT" > simulate/tb_debug.h