rtl cache refactory

2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
--- a/hw/rtl/interfaces/VX_wb_if.v
+++ b/hw/rtl/interfaces/VX_wb_if.v
@@ -5,12 +5,12 @@

 interface VX_wb_if ();

-    wire [`NUM_THREADS-1:0][31:0]	write_data; 
-    wire [31:0]                     wb_pc;
+    wire [`NUM_THREADS-1:0]         valid;
+    wire [`NUM_THREADS-1:0][31:0]	data; 
+    wire [`NW_BITS-1:0]             warp_num;
    wire [4:0]                      rd;
-    wire [1:0]                      wb;
-    wire [`NUM_THREADS-1:0]         wb_valid;
-    wire [`NW_BITS-1:0]             wb_warp_num;
+    wire [1:0]                      wb;    
+    wire [31:0]                     pc;    

 endinterface