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rtl cache refactory

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This commit is contained in:
Blaise Tine
2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
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9
hw/rtl/VX_fetch.v
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@@ -22,13 +22,7 @@ module VX_fetch (
wire[31:0] warp_pc;
wire scheduled_warp;
wire pipe_stall;
// Only reason this is there is because there is a hidden assumption that decode is exactly after fetch
// Locals
assign pipe_stall = schedule_delay || icache_stage_delay;
wire pipe_stall = schedule_delay || icache_stage_delay;
VX_warp_sched warp_sched (
.clk (clk),
@@ -97,6 +91,7 @@ module VX_fetch (
assign fe_inst_meta_fi.valid = thread_mask;
assign fe_inst_meta_fi.instruction = 32'h0;
assign fe_inst_meta_fi.inst_pc = warp_pc;
`DEBUG_BEGIN
wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);