minor updates

2022-02-01 22:51:33 -05:00
parent d48f1c1c5f
commit a06812f93f
21 changed files with 73 additions and 70 deletions
--- a/hw/rtl/VX_alu_unit.sv
+++ b/hw/rtl/VX_alu_unit.sv
@@ -223,7 +223,7 @@ module VX_alu_unit #(
    // can accept new request?
    assign alu_req_if.ready = ready_in;

-`ifdef DBG_TRACE_PIPELINE
+`ifdef DBG_TRACE_CORE_PIPELINE
    always @(posedge clk) begin
        if (branch_ctl_if.valid) begin
            dpi_trace("%d: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h (#%0d)\n",