cache pipeline optimization

2021-01-17 17:19:52 -08:00
parent ed216ab39d
commit a046bd7a73
11 changed files with 129 additions and 166 deletions
--- a/hw/rtl/cache/VX_miss_resrv.v
+++ b/hw/rtl/cache/VX_miss_resrv.v
@@ -186,9 +186,7 @@ module VX_miss_resrv #(
        if (reset) begin
            schedule_valid_n_r = 0;
        end else begin
-            if (restore) begin
-                schedule_valid_n_r = enqueue_as_ready;
-            end else if (lookup_ready) begin
+            if (lookup_ready) begin
                schedule_valid_n_r = schedule_valid_r || (schedule_addr_r == lookup_addr);
            end else if (schedule) begin
                schedule_valid_n_r = ready_table[schedule_n_ptr];