code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/interfaces/VX_mem_rsp_if.v
+++ b/hw/rtl/interfaces/VX_mem_rsp_if.v
@@ -11,7 +11,21 @@ interface VX_mem_rsp_if #(
    wire                    valid;    
    wire [DATA_WIDTH-1:0]   data;
    wire [TAG_WIDTH-1:0]    tag;  
-    wire                    ready;      
+    wire                    ready;  
+
+    modport master (
+        output valid,
+        output data,
+        output tag,
+        input  ready
+    );
+
+    modport slave (
+        input  valid,
+        input  data,
+        input  tag,
+        output ready
+    );    

 endinterface