code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/interfaces/VX_branch_ctl_if.v
+++ b/hw/rtl/interfaces/VX_branch_ctl_if.v
@@ -10,6 +10,20 @@ interface VX_branch_ctl_if ();
    wire                taken;
    wire [31:0]         dest;

+    modport master (
+        output valid,    
+        output wid,
+        output taken,
+        output dest
+    );
+
+    modport slave (
+        input valid,   
+        input wid,
+        input taken,
+        input dest
+    );
+
 endinterface

 `endif