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code refactoring for Vivado, sv2v, and yosys compatibility

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This commit is contained in:
Blaise Tine
2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
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38
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -22,6 +22,44 @@ interface VX_alu_req_if ();
wire wb;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output next_PC,
output op_type,
output op_mod,
output use_PC,
output use_imm,
output imm,
output tid,
output rs1_data,
output rs2_data,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input next_PC,
input op_type,
input op_mod,
input use_PC,
input use_imm,
input imm,
input tid,
input rs1_data,
input rs2_data,
input rd,
input wb,
output ready
);
endinterface
`endif

14
hw/rtl/interfaces/VX_branch_ctl_if.v
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@@ -10,6 +10,20 @@ interface VX_branch_ctl_if ();
wire taken;
wire [31:0] dest;
modport master (
output valid,
output wid,
output taken,
output dest
);
modport slave (
input valid,
input wid,
input taken,
input dest
);
endinterface
`endif

10
hw/rtl/interfaces/VX_cmt_to_csr_if.v
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@@ -8,6 +8,16 @@ interface VX_cmt_to_csr_if ();
wire valid;
wire [$clog2(`NUM_THREADS+1)-1:0] commit_size;
modport master (
output valid,
output commit_size
);
modport slave (
input valid,
input commit_size
);
endinterface
`endif

26
hw/rtl/interfaces/VX_commit_if.v
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@@ -13,7 +13,31 @@ interface VX_commit_if ();
wire [`NR_BITS-1:0] rd;
wire wb;
wire eop;
wire ready;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output data,
output rd,
output wb,
output eop,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input data,
input rd,
input wb,
input eop,
output ready
);
endinterface

30
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -17,6 +17,36 @@ interface VX_csr_req_if ();
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output op_type,
output addr,
output rs1_data,
output use_imm,
output imm,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input op_type,
input addr,
input rs1_data,
input use_imm,
input imm,
input rd,
input wb,
output ready
);
endinterface

20
hw/rtl/interfaces/VX_dcache_req_if.v
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@@ -17,6 +17,26 @@ interface VX_dcache_req_if #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
modport master (
output valid,
output rw,
output byteen,
output addr,
output data,
output tag,
input ready
);
modport slave (
input valid,
input rw,
input byteen,
input addr,
input data,
input tag,
output ready
);
endinterface
`endif

16
hw/rtl/interfaces/VX_dcache_rsp_if.v
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@@ -15,6 +15,22 @@ interface VX_dcache_rsp_if #(
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output tmask,
output data,
output tag,
input ready
);
modport slave (
input valid,
input tmask,
input data,
input tag,
output ready
);
endinterface
`endif

38
hw/rtl/interfaces/VX_decode_if.v
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@@ -22,6 +22,44 @@ interface VX_decode_if ();
wire [`NR_BITS-1:0] rs3;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output ex_type,
output op_type,
output op_mod,
output wb,
output use_PC,
output use_imm,
output imm,
output rd,
output rs1,
output rs2,
output rs3,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input ex_type,
input op_type,
input op_mod,
input wb,
input use_PC,
input use_imm,
input imm,
input rd,
input rs1,
input rs2,
input rs3,
output ready
);
endinterface
`endif

8
hw/rtl/interfaces/VX_fetch_to_csr_if.v
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@@ -7,6 +7,14 @@ interface VX_fetch_to_csr_if ();
wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
modport master (
output thread_masks
);
modport slave (
input thread_masks
);
endinterface
`endif

30
hw/rtl/interfaces/VX_fpu_req_if.v
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@@ -18,6 +18,36 @@ interface VX_fpu_req_if ();
wire wb;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output op_type,
output op_mod,
output rs1_data,
output rs2_data,
output rs3_data,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input op_type,
input op_mod,
input rs1_data,
input rs2_data,
input rs3_data,
input rd,
input wb,
output ready
);
endinterface
`endif

16
hw/rtl/interfaces/VX_fpu_to_csr_if.v
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@@ -12,6 +12,22 @@ interface VX_fpu_to_csr_if ();
wire [`NW_BITS-1:0] read_wid;
wire [`INST_FRM_BITS-1:0] read_frm;
modport master (
output write_enable,
output write_wid,
output write_fflags,
output read_wid,
input read_frm
);
modport slave (
input write_enable,
input write_wid,
input write_fflags,
input read_wid,
output read_frm
);
endinterface
`endif

16
hw/rtl/interfaces/VX_gpr_req_if.v
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@@ -8,7 +8,21 @@ interface VX_gpr_req_if ();
wire [`NW_BITS-1:0] wid;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire [`NR_BITS-1:0] rs3;
modport master (
output wid,
output rs1,
output rs2,
output rs3
);
modport slave (
input wid,
input rs1,
input rs2,
input rs3
);
endinterface

12
hw/rtl/interfaces/VX_gpr_rsp_if.v
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@@ -9,6 +9,18 @@ interface VX_gpr_rsp_if ();
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
modport master (
output rs1_data,
output rs2_data,
output rs3_data
);
modport slave (
input rs1_data,
input rs2_data,
input rs3_data
);
endinterface
`endif

30
hw/rtl/interfaces/VX_gpu_req_if.v
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@@ -20,6 +20,36 @@ interface VX_gpu_req_if();
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output next_PC,
output op_type,
output tid,
output rs1_data,
output rs2_data,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input next_PC,
input op_type,
input tid,
input rs1_data,
input rs2_data,
input rd,
input wb,
output ready
);
endinterface
`endif

54
hw/rtl/interfaces/VX_ibuffer_if.v
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@@ -20,14 +20,62 @@ interface VX_ibuffer_if ();
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire ready;
// scoreboard forwarding
wire [`NR_BITS-1:0] rd_n;
wire [`NR_BITS-1:0] rs1_n;
wire [`NR_BITS-1:0] rs2_n;
wire [`NR_BITS-1:0] rs3_n;
wire [`NW_BITS-1:0] wid_n;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output ex_type,
output op_type,
output op_mod,
output wb,
output use_PC,
output use_imm,
output imm,
output rd,
output rs1,
output rs2,
output rs3,
output rd_n,
output rs1_n,
output rs2_n,
output rs3_n,
output wid_n,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input ex_type,
input op_type,
input op_mod,
input wb,
input use_PC,
input use_imm,
input imm,
input rd,
input rs1,
input rs2,
input rs3,
input rd_n,
input rs1_n,
input rs2_n,
input rs3_n,
input wid_n,
output ready
);
endinterface

14
hw/rtl/interfaces/VX_icache_req_if.v
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@@ -13,6 +13,20 @@ interface VX_icache_req_if #(
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output addr,
output tag,
input ready
);
modport slave (
input valid,
input addr,
input tag,
output ready
);
endinterface
`endif

16
hw/rtl/interfaces/VX_icache_rsp_if.v
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@@ -11,7 +11,21 @@ interface VX_icache_rsp_if #(
wire valid;
wire [`WORD_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
wire ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface

16
hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -11,6 +11,22 @@ interface VX_ifetch_req_if ();
wire [31:0] PC;
wire ready;
modport master (
output valid,
output tmask,
output wid,
output PC,
input ready
);
modport slave (
input valid,
input tmask,
input wid,
input PC,
output ready
);
endinterface
`endif

18
hw/rtl/interfaces/VX_ifetch_rsp_if.v
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@@ -12,6 +12,24 @@ interface VX_ifetch_rsp_if ();
wire [31:0] data;
wire ready;
modport master (
output valid,
output tmask,
output wid,
output PC,
output data,
input ready
);
modport slave (
input valid,
input tmask,
input wid,
input PC,
input data,
output ready
);
endinterface
`endif

10
hw/rtl/interfaces/VX_join_if.v
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@@ -8,6 +8,16 @@ interface VX_join_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
modport master (
output valid,
output wid
);
modport slave (
input valid,
input wid
);
endinterface
`endif

30
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -18,6 +18,36 @@ interface VX_lsu_req_if ();
wire wb;
wire ready;
modport master (
output valid,
output wid,
output tmask,
output PC,
output op_type,
output is_fence,
output store_data,
output base_addr,
output offset,
output rd,
output wb,
input ready
);
modport slave (
input valid,
input wid,
input tmask,
input PC,
input op_type,
input is_fence,
input store_data,
input base_addr,
input offset,
input rd,
input wb,
output ready
);
endinterface
`endif

20
hw/rtl/interfaces/VX_mem_req_if.v
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@@ -18,6 +18,26 @@ interface VX_mem_req_if #(
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output rw,
output byteen,
output addr,
output data,
output tag,
input ready
);
modport slave (
input valid,
input rw,
input byteen,
input addr,
input data,
input tag,
output ready
);
endinterface
`endif

16
hw/rtl/interfaces/VX_mem_rsp_if.v
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@@ -11,7 +11,21 @@ interface VX_mem_rsp_if #(
wire valid;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
wire ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface

22
hw/rtl/interfaces/VX_perf_cache_if.v
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@@ -14,6 +14,28 @@ interface VX_perf_cache_if ();
wire [`PERF_CTR_BITS-1:0] pipe_stalls;
wire [`PERF_CTR_BITS-1:0] crsp_stalls;
modport master (
output reads,
output writes,
output read_misses,
output write_misses,
output bank_stalls,
output mshr_stalls,
output pipe_stalls,
output crsp_stalls
);
modport slave (
input reads,
input writes,
input read_misses,
input write_misses,
input bank_stalls,
input mshr_stalls,
input pipe_stalls,
input crsp_stalls
);
endinterface
`endif

44
hw/rtl/interfaces/VX_perf_memsys_if.v
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@@ -28,6 +28,50 @@ interface VX_perf_memsys_if ();
wire [`PERF_CTR_BITS-1:0] mem_stalls;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output icache_reads,
output icache_read_misses,
output icache_pipe_stalls,
output icache_crsp_stalls,
output dcache_reads,
output dcache_writes,
output dcache_read_misses,
output dcache_write_misses,
output dcache_bank_stalls,
output dcache_mshr_stalls,
output dcache_pipe_stalls,
output dcache_crsp_stalls,
output smem_reads,
output smem_writes,
output smem_bank_stalls,
output mem_reads,
output mem_writes,
output mem_stalls,
output mem_latency
);
modport slave (
input icache_reads,
input icache_read_misses,
input icache_pipe_stalls,
input icache_crsp_stalls,
input dcache_reads,
input dcache_writes,
input dcache_read_misses,
input dcache_write_misses,
input dcache_bank_stalls,
input dcache_mshr_stalls,
input dcache_pipe_stalls,
input dcache_crsp_stalls,
input smem_reads,
input smem_writes,
input smem_bank_stalls,
input mem_reads,
input mem_writes,
input mem_stalls,
input mem_latency
);
endinterface
`endif

28
hw/rtl/interfaces/VX_perf_pipeline_if.v
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@@ -4,15 +4,41 @@
`include "VX_define.vh"
interface VX_perf_pipeline_if ();
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] lsu_stalls;
wire [`PERF_CTR_BITS-1:0] csr_stalls;
wire [`PERF_CTR_BITS-1:0] alu_stalls;
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
`ifdef EXT_F_ENABLE
wire [`PERF_CTR_BITS-1:0] fpu_stalls;
`endif
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
modport master (
output ibf_stalls,
output scb_stalls,
output lsu_stalls,
output csr_stalls,
output alu_stalls,
`ifdef EXT_F_ENABLE
output fpu_stalls,
`endif
output gpu_stalls
);
modport slave (
input ibf_stalls,
input scb_stalls,
input lsu_stalls,
input csr_stalls,
input alu_stalls,
`ifdef EXT_F_ENABLE
input fpu_stalls,
`endif
input gpu_stalls
);
endinterface
`endif

18
hw/rtl/interfaces/VX_warp_ctl_if.v
View File

@@ -12,6 +12,24 @@ interface VX_warp_ctl_if ();
gpu_barrier_t barrier;
gpu_split_t split;
modport master (
output valid,
output wid,
output tmc,
output wspawn,
output barrier,
output split
);
modport slave (
input valid,
input wid,
input tmc,
input wspawn,
input barrier,
input split
);
endinterface
`endif

26
hw/rtl/interfaces/VX_writeback_if.v
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@@ -6,16 +6,36 @@
interface VX_writeback_if ();
wire valid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data;
wire eop;
wire eop;
wire ready;
modport master (
output valid,
output tmask,
output wid,
output PC,
output rd,
output data,
output eop,
input ready
);
modport slave (
input valid,
input tmask,
input wid,
input PC,
input rd,
input data,
input eop,
output ready
);
endinterface
`endif

12
hw/rtl/interfaces/VX_wstall_if.v
View File

@@ -9,6 +9,18 @@ interface VX_wstall_if();
wire [`NW_BITS-1:0] wid;
wire stalled;
modport master (
output valid,
output wid,
output stalled
);
modport slave (
input valid,
input wid,
input stalled
);
endinterface
`endif