code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/VX_mem_arb.v
+++ b/hw/rtl/VX_mem_arb.v
@@ -10,9 +10,9 @@ module VX_mem_arb #(
    parameter BUFFERED_RSP  = 0,
    parameter TYPE          = "P",
    
-    localparam DATA_SIZE     = (DATA_WIDTH / 8),
-    localparam LOG_NUM_REQS  = `CLOG2(NUM_REQS),
-    localparam TAG_OUT_WIDTH = TAG_IN_WIDTH + LOG_NUM_REQS
+    parameter DATA_SIZE     = (DATA_WIDTH / 8),
+    parameter LOG_NUM_REQS  = `CLOG2(NUM_REQS),
+    parameter TAG_OUT_WIDTH = TAG_IN_WIDTH + LOG_NUM_REQS
 ) (
    input wire clk,
    input wire reset,