code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00
parent 9b04f3d9d6
commit 9f34b2944c
97 changed files with 1435 additions and 666 deletions
--- a/hw/rtl/VX_ibuffer.v
+++ b/hw/rtl/VX_ibuffer.v
@@ -7,10 +7,10 @@ module VX_ibuffer #(
    input wire reset,

    // inputs
-    VX_decode_if  decode_if,  
+    VX_decode_if.slave  decode_if,  

    // outputs
-    VX_ibuffer_if ibuffer_if
+    VX_ibuffer_if.master ibuffer_if
 );

    `UNUSED_PARAM (CORE_ID)