Vector changes

simX/include/core.h

@@ -37,6 +37,8 @@ namespace Harp {
   public:
     Reg(): cpuId(0), regNum(0), val(0) {}
     Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {}
+    Reg(Word c, Word n, T v): cpuId(c), regNum(n), val(v) {}
+
 
     Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; }
 
@@ -47,9 +49,10 @@ namespace Harp {
       val &= mask;
     }
 
+    T val;
   private:
     Word cpuId, regNum;
-    T val;
+//    T val;
 
 #ifdef EMU_INSTRUMENTATION
     /* Access size here is 8, representing the register size of 64-bit cores. */
@@ -86,6 +89,14 @@ namespace Harp {
     Word pc;
   };
 
+  struct vtype
+  {
+    int vill;
+    int vediv;
+    int vsew;
+    int vlmul;
+  };
+
   class Warp;
 
   class Core {
@@ -172,6 +183,13 @@ namespace Harp {
     std::vector<Word> shadowReg;
     std::vector<bool> shadowPReg;
 
+    //Vector CSR
+    struct vtype vtype; //both of them are XLEN WIDE
+    int vl;    //both of them are XLEN WIDE
+    Word VLEN; //Total vector length
+
+    std::vector<std::vector<Reg<char*>>> vreg; // 32 vector registers
+
     bool interruptEnable, shadowInterruptEnable, supervisorMode, 
          shadowSupervisorMode, spawned;
 

simX/include/debug.h

@@ -5,14 +5,14 @@
 #define __DEBUG_H
 
 // #define USE_DEBUG 9
-#define USE_DEBUG -1
+#define USE_DEBUG 3
 
 #ifdef USE_DEBUG
 #include <iostream>
 
 #define D(lvl, x) do { \
   using namespace std; \
-  if ((lvl) <= USE_DEBUG) { \
+  if ((lvl) == USE_DEBUG) { \
     cout << "DEBUG " << __FILE__ << ':' << dec << __LINE__ << ": " \
          << x << endl; \
   } \

simX/include/enc.h

@@ -60,11 +60,15 @@ namespace Harp {
     Size inst_s, opcode_s, reg_s, func3_s;
     Size shift_opcode, shift_rd, shift_rs1, shift_rs2, shift_func3, shift_func7;
     Size shift_j_u_immed, shift_s_b_immed, shift_i_immed;
+    //Vector
+    Size shift_vset, shift_vset_immed, shift_vmask, shift_vmop, shift_vnf, shift_func6;
+    Size vmask_s, mop_s;
+
 
 
 
     Word reg_mask, func3_mask, func7_mask, opcode_mask, i_immed_mask, 
-          s_immed_mask, b_immed_mask, u_immed_mask, j_immed_mask;
+          s_immed_mask, b_immed_mask, u_immed_mask, j_immed_mask, v_immed_mask, func6_mask;
 
   };
 

simX/include/harpfloat.h

@@ -81,7 +81,7 @@ namespace Harp {
 
       bool sign(d < 0);
 
-      bool inf(isinf(d)), zero(d == 0.0);
+      bool inf(std::isinf(d)), zero(d == 0.0);
       int exp;
 
       if (!inf && !zero) exp = floor(log2(fabs(d)));

simX/include/instruction.h

@@ -6,6 +6,7 @@
 
 #include <map>
 #include <iostream>
+#include <math.h>
 
 #include "types.h"
 #include "trace.h"
@@ -29,10 +30,13 @@ namespace Harp {
       TRAP     = 0x7f,
       FENCE    = 0x0f,
       PJ_INST  = 0x7b,
-      GPGPU    = 0x6b
+      GPGPU    = 0x6b,
+      VSET_ARITH = 0x57,
+      VL       = 0x7,
+      VS       = 0x27,
    };
 
-  enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE};
+  enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE, V_TYPE};
 
   // We build a table of instruction information out of this.
   struct InstTableEntry_t {
@@ -58,7 +62,10 @@ namespace Harp {
     {Opcode::TRAP,       {"TRAP"  , true , false, false, false, InstType::I_TYPE }},
     {Opcode::FENCE,      {"fence" , true , false, false, false, InstType::I_TYPE }},
     {Opcode::PJ_INST,    {"pred j", true , false, false, false, InstType::R_TYPE }},
-    {Opcode::GPGPU,      {"gpgpu" , false, false, false, false, InstType::R_TYPE }}
+    {Opcode::GPGPU,      {"gpgpu" , false, false, false, false, InstType::R_TYPE }},
+    {Opcode::VSET_ARITH, {"vsetvl" , false, false, false, false, InstType::V_TYPE }}, 
+    {Opcode::VL,         {"vl" , false, false, false, false, InstType::V_TYPE }}, 
+    {Opcode::VS,         {"vs" , false, false, false, false, InstType::V_TYPE }}  
   };
 
   static const Size MAX_REG_SOURCES(3);
@@ -94,6 +101,16 @@ namespace Harp {
     Word *setSrcImm  () { immsrcPresent = true; immsrc = 0xa5; return &immsrc;}
     void  setSrcImm  (Word srcImm) { immsrcPresent = true; immsrc = srcImm; }
     void  setImmRef  (Ref &r) { refLiteral = &r; }
+    void  setVsetImm (Word vset_imm) { if(vset_imm) vsetImm = true; else vsetImm = false; }
+    void  setVlsWidth (Word width) { vlsWidth = width; }
+    void  setVmop( Word mop) { vMop = mop; }
+    void  setVnf(Word nf) { vNf = nf; }
+    void  setVmask(Word mask) { vmask = mask; }
+    void  setVs3(Word vs) { vs3 = vs; }
+    void  setvlmul(Word lmul) { vlmul = pow(2, lmul); }
+    void  setvsew(Word sew) { vsew = pow(2, 3+sew); }
+    void  setvediv(Word ediv) { vediv = pow(2,ediv); }
+    void  setFunc6(Word func6) { this->func6 = func6; }
 
     /* Getters used by encoders. */
     Opcode getOpcode() const { return op; }
@@ -111,6 +128,16 @@ namespace Harp {
     Word getImm() const { return immsrc; }
     bool hasRefLiteral() const { return refLiteral != NULL; }
     Ref *getRefLiteral() const { return refLiteral; }
+    bool getVsetImm() const { return vsetImm; }
+    Word getVlsWidth() const { return vlsWidth; }
+    Word getVmop() const { return vMop; }
+    Word getvNf() const { return vNf; }
+    bool getVmask() const { return vmask; }
+    Word getVs3() const { return vs3; }
+    Word getvlmul() const { return vlmul; }
+    Word getvsew() const { return vsew; }
+    Word getvediv() const { return vediv; }
+
 
     /* Getters used as table lookup. */
     bool hasRelImm() const { return (*(instTable.find(op))).second.relAddress; }
@@ -129,6 +156,10 @@ namespace Harp {
     RegNum rdest, pdest;
     Ref *refLiteral;
 
+    //Vector
+    bool vsetImm, vmask;
+    Word vlsWidth, vMop, vNf, vs3, vlmul, vsew, vediv, func6;
+
   public: