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adding dram writeenable support + scheduler bug fixes

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This commit is contained in:
Blaise Tine
2020-05-27 19:00:23 -04:00
parent a9f896b4f3
commit 9e5885b820
96 changed files with 21656 additions and 86621 deletions
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89
hw/rtl/VX_dmem_ctrl.v
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@@ -25,21 +25,21 @@ module VX_dmem_ctrl # (
VX_cache_dram_rsp_if icache_dram_rsp_if
);
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.NUM_REQUESTS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) dcache_core_req_qual_if(), smem_core_req_if();
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS(`CORE_TAG_ID_BITS)
.NUM_REQUESTS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) dcache_core_rsp_qual_if(), smem_core_rsp_if();
// use "case equality" to handle uninitialized entry
wire smem_select = ((dcache_core_req_if.core_req_addr[0][31:24] == `SHARED_MEM_TOP_ADDR) === 1'b1);
wire smem_select = ((dcache_core_req_if.core_req_addr[0] >= `BYTE_TO_WORD_ADDR(`SHARED_MEM_BASE_ADDR, `DWORD_SIZE)) === 1'b1);
VX_dcache_io_arb dcache_io_arb (
.io_select (smem_select),
@@ -59,20 +59,20 @@ module VX_dmem_ctrl # (
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQUESTS (`SNUM_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.REQQ_SIZE (`SREQQ_SIZE),
.MRVQ_SIZE (`SMRVQ_SIZE),
.DFPQ_SIZE (`SDFPQ_SIZE),
.CREQ_SIZE (`SCREQ_SIZE),
.MRVQ_SIZE (1),
.DFPQ_SIZE (0),
.SNRQ_SIZE (0),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (`SDWBQ_SIZE),
.DFQQ_SIZE (`SDFQQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.DWBQ_SIZE (0),
.DFQQ_SIZE (0),
.PRFQ_SIZE (0),
.PRFQ_STRIDE (0),
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (0),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS (`CORE_TAG_ID_BITS),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) gpu_smem (
.clk (clk),
@@ -80,8 +80,8 @@ module VX_dmem_ctrl # (
// Core request
.core_req_valid (smem_core_req_if.core_req_valid),
.core_req_read (smem_core_req_if.core_req_read),
.core_req_write (smem_core_req_if.core_req_write),
.core_req_rw (smem_core_req_if.core_req_rw),
.core_req_byteen (smem_core_req_if.core_req_byteen),
.core_req_addr (smem_core_req_if.core_req_addr),
.core_req_data (smem_core_req_if.core_req_data),
.core_req_tag (smem_core_req_if.core_req_tag),
@@ -94,21 +94,22 @@ module VX_dmem_ctrl # (
.core_rsp_ready (smem_core_rsp_if.core_rsp_ready),
// DRAM request
`UNUSED_PIN (dram_req_read),
`UNUSED_PIN (dram_req_write),
`UNUSED_PIN (dram_req_valid),
`UNUSED_PIN (dram_req_rw),
`UNUSED_PIN (dram_req_byteen),
`UNUSED_PIN (dram_req_addr),
`UNUSED_PIN (dram_req_data),
`UNUSED_PIN (dram_req_tag),
.dram_req_ready (1'b0),
.dram_req_ready (0),
// DRAM response
.dram_rsp_valid (1'b0),
.dram_rsp_valid (0),
.dram_rsp_data (0),
.dram_rsp_tag (`SDRAM_TAG_WIDTH'(0)),
.dram_rsp_tag (0),
`UNUSED_PIN (dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_valid (0),
.snp_req_addr (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
@@ -116,7 +117,7 @@ module VX_dmem_ctrl # (
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
.snp_rsp_ready (0),
// Snoop forward out
`UNUSED_PIN (snp_fwdout_valid),
@@ -138,7 +139,7 @@ module VX_dmem_ctrl # (
.WORD_SIZE (`DWORD_SIZE),
.NUM_REQUESTS (`DNUM_REQUESTS),
.STAGE_1_CYCLES (`DSTAGE_1_CYCLES),
.REQQ_SIZE (`DREQQ_SIZE),
.CREQ_SIZE (`DCREQ_SIZE),
.MRVQ_SIZE (`DMRVQ_SIZE),
.DFPQ_SIZE (`DDFPQ_SIZE),
.SNRQ_SIZE (`DSNRQ_SIZE),
@@ -150,8 +151,8 @@ module VX_dmem_ctrl # (
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS (`CORE_TAG_ID_BITS),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) gpu_dcache (
@@ -160,8 +161,8 @@ module VX_dmem_ctrl # (
// Core req
.core_req_valid (dcache_core_req_qual_if.core_req_valid),
.core_req_read (dcache_core_req_qual_if.core_req_read),
.core_req_write (dcache_core_req_qual_if.core_req_write),
.core_req_rw (dcache_core_req_qual_if.core_req_rw),
.core_req_byteen (dcache_core_req_qual_if.core_req_byteen),
.core_req_addr (dcache_core_req_qual_if.core_req_addr),
.core_req_data (dcache_core_req_qual_if.core_req_data),
.core_req_tag (dcache_core_req_qual_if.core_req_tag),
@@ -174,8 +175,9 @@ module VX_dmem_ctrl # (
.core_rsp_ready (dcache_core_rsp_qual_if.core_rsp_ready),
// DRAM request
.dram_req_read (dcache_dram_req_if.dram_req_read),
.dram_req_write (dcache_dram_req_if.dram_req_write),
.dram_req_valid (dcache_dram_req_if.dram_req_valid),
.dram_req_rw (dcache_dram_req_if.dram_req_rw),
.dram_req_byteen (dcache_dram_req_if.dram_req_byteen),
.dram_req_addr (dcache_dram_req_if.dram_req_addr),
.dram_req_data (dcache_dram_req_if.dram_req_data),
.dram_req_tag (dcache_dram_req_if.dram_req_tag),
@@ -218,7 +220,7 @@ module VX_dmem_ctrl # (
.WORD_SIZE (`IWORD_SIZE),
.NUM_REQUESTS (`INUM_REQUESTS),
.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
.REQQ_SIZE (`IREQQ_SIZE),
.CREQ_SIZE (`ICREQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (0),
@@ -230,8 +232,8 @@ module VX_dmem_ctrl # (
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (1),
.WRITE_ENABLE (0),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.CORE_TAG_ID_BITS (`CORE_TAG_ID_BITS),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) gpu_icache (
.clk (clk),
@@ -239,8 +241,8 @@ module VX_dmem_ctrl # (
// Core request
.core_req_valid (icache_core_req_if.core_req_valid),
.core_req_read (icache_core_req_if.core_req_read),
.core_req_write (icache_core_req_if.core_req_write),
.core_req_rw (icache_core_req_if.core_req_rw),
.core_req_byteen (icache_core_req_if.core_req_byteen),
.core_req_addr (icache_core_req_if.core_req_addr),
.core_req_data (icache_core_req_if.core_req_data),
.core_req_tag (icache_core_req_if.core_req_tag),
@@ -253,8 +255,9 @@ module VX_dmem_ctrl # (
.core_rsp_ready (icache_core_rsp_if.core_rsp_ready),
// DRAM Req
.dram_req_read (icache_dram_req_if.dram_req_read),
.dram_req_write (icache_dram_req_if.dram_req_write),
.dram_req_valid (icache_dram_req_if.dram_req_valid),
.dram_req_rw (icache_dram_req_if.dram_req_rw),
.dram_req_byteen (icache_dram_req_if.dram_req_byteen),
.dram_req_addr (icache_dram_req_if.dram_req_addr),
.dram_req_data (icache_dram_req_if.dram_req_data),
.dram_req_tag (icache_dram_req_if.dram_req_tag),
@@ -267,7 +270,7 @@ module VX_dmem_ctrl # (
.dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_valid (0),
.snp_req_addr (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
@@ -275,7 +278,7 @@ module VX_dmem_ctrl # (
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
.snp_rsp_ready (0),
// Snoop forward out
`UNUSED_PIN (snp_fwdout_valid),