Finished Cache Integration
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@@ -33,10 +33,10 @@ module VX_shared_memory_block (
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// wire[3:0][31:0] write_bit_mask;
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// assign write_bit_mask[0] = (we == 2'b00) ? 0 : {32{1'b1}};
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// assign write_bit_mask[1] = (we == 2'b01) ? 0 : {32{1'b1}};
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// assign write_bit_mask[2] = (we == 2'b10) ? 0 : {32{1'b1}};
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// assign write_bit_mask[3] = (we == 2'b11) ? 0 : {32{1'b1}};
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// assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
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// assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
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// assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
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// assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
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// // Using ASIC MEM
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// /* verilator lint_off PINCONNECTEMPTY */
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