Finished Cache Integration

rtl/Vortex.v

@@ -1,17 +1,29 @@
 
 `include "VX_define.v"
 
+
 module Vortex(
 	input  wire           clk,
 	input  wire           reset,
 	input  wire[31:0] icache_response_instruction,
 	output wire[31:0] icache_request_pc_address,
+	// Req
+    output reg [31:0]  o_m_addr,
+    output reg         o_m_valid,
+    output reg [31:0]  o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
+    output reg         o_m_read_or_write,
+
+    // Rsp
+    input  wire [31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
+    input  wire        i_m_ready,
+	// Remove Start
 	input  wire[31:0]     in_cache_driver_out_data[`NT_M1:0],
 	output wire[31:0]     out_cache_driver_in_address[`NT_M1:0],
 	output wire[2:0]      out_cache_driver_in_mem_read,
 	output wire[2:0]      out_cache_driver_in_mem_write,
 	output wire           out_cache_driver_in_valid[`NT_M1:0],
 	output wire[31:0]     out_cache_driver_in_data[`NT_M1:0],
+	// Remove end
 	output wire           out_ebreak
 	);
 
@@ -35,6 +47,27 @@ assign out_cache_driver_in_mem_write = `NO_MEM_WRITE;
 VX_dcache_response_inter VX_dcache_rsp();
 VX_dcache_request_inter  VX_dcache_req();
 
+
+VX_dram_req_rsp_inter    VX_dram_req_rsp();
+
+assign o_m_addr          = VX_dram_req_rsp.o_m_addr;
+assign o_m_valid         = VX_dram_req_rsp.o_m_valid;
+assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
+
+assign VX_dram_req_rsp.i_m_ready = i_m_ready;
+
+genvar curr_bank;
+genvar curr_word;
+for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank = curr_bank + 1) begin
+
+	for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
+
+		assign o_m_writedata[curr_bank][curr_word]                = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
+		assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
+
+	end
+end
+
 // Icache Interface
 
 VX_icache_response_inter icache_response_fe();
@@ -108,9 +141,11 @@ VX_back_end vx_back_end(
 
 
 VX_dmem_controller VX_dmem_controller(
-	.clk          (clk),
-	.VX_dcache_req(VX_dcache_req),
-	.VX_dcache_rsp(VX_dcache_rsp)
+	.clk            (clk),
+	.reset          (reset),
+	.VX_dram_req_rsp(VX_dram_req_rsp),
+	.VX_dcache_req  (VX_dcache_req),
+	.VX_dcache_rsp  (VX_dcache_rsp)
 	);
 // VX_csr_handler vx_csr_handler(
 // 		.clk                  (clk),