updated from GT repo

hw/unit_tests/cache/cachesim.cpp

@@ -58,6 +58,7 @@ void CacheSim::reset() {
 }
 
 void CacheSim::step() {
+  //std::cout << timestamp << ": [sim] step()" << std::endl;
   //toggle clock
   cache_->clk = 0;
   this->eval();
@@ -69,6 +70,7 @@ void CacheSim::step() {
   this->eval_reqs();
   this->eval_rsps();
   this->eval_dram_bus();
+  timestamp++;
 }
 
 void CacheSim::eval() {
@@ -80,18 +82,20 @@ void CacheSim::eval() {
 }
 
 void CacheSim::run(){
-#ifndef NDEBUG
+//#ifndef NDEBUG
-  std::cout << timestamp << ": [sim] run()" << std::endl;
+  
-#endif
+//#endif
   this->step();
 
   int valid = 300; 
   
   while (valid > -1) {
+
       this->step();
       if(!cache_->core_req_valid && !cache_->core_rsp_valid){
         valid--; 
       }
+      this->display_hit_miss();
   }
 }
 
@@ -251,12 +255,14 @@ void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
   rsp[1] = cache_->core_rsp_data[1];
   rsp[2] = cache_->core_rsp_data[2];
   rsp[3] = cache_->core_rsp_data[3];
+
   //std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
   //std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
   //std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; 
 }
 
 void CacheSim::get_core_req(){
+  //std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl; 
   char check = cache_->core_req_valid;
   std::cout << std::hex << "core_req_valid: " << check << std::endl;
   std::cout << std::hex << "core_req_data[0]: " << cache_->core_req_data[0] << std::endl;
@@ -282,3 +288,7 @@ void CacheSim::get_dram_rsp(){
   std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
 }
 
+void CacheSim::display_hit_miss(){
+  std::cout << std::hex << "Misses: " << cache_->misses << std::endl; 
+}
+

hw/unit_tests/cache/cachesim.h

@@ -52,6 +52,7 @@ public:
   void clear_req(); 
   void send_req(core_req_t *req);
   bool assert_equal(unsigned int* data, unsigned int tag);
+  //void time_analyisis 
 
   //display funcs
 
@@ -61,6 +62,7 @@ public:
   bool get_core_req_ready();
   bool get_core_rsp_ready();
   void get_dram_rsp();
+  void display_hit_miss(); 
 
 
 private:  

hw/unit_tests/cache/testbench.cpp

@@ -5,13 +5,8 @@
 
 #define VCD_OUTPUT 1
 
-int main(int argc, char **argv)
-{
-  //init
-  RAM ram;
-	CacheSim cachesim;
-  cachesim.attach_ram(&ram);
 
+int REQ_RSP(CacheSim *sim){ //verified
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};
@@ -34,21 +29,209 @@ int main(int argc, char **argv)
   read->data = addr; 
   read->tag = 0xff;
   
-	// reset the device
+  // reset the device
-  cachesim.reset();
+  sim->reset();
 
   //queue reqs
-  cachesim.send_req(write);
+  sim->send_req(write);
-  cachesim.send_req(read);
+  sim->send_req(read);
 
-  cachesim.run(); 
+  sim->run();
 
-  bool check = cachesim.assert_equal(data, write->tag);
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int HIT_1(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0x11;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0x22;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+int MISS_1(CacheSim *sim){
+  unsigned int addr1[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int addr2[4] = {0x12244444, 0xabb0bbbb, 0xcddd0ddd, 0xe0444444};
+  unsigned int addr3[4] = {0x12888888, 0xa0bbbbbb, 0xcddddd0d, 0xe4444440};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr1; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read1 = new core_req_t;
+  read1->valid = 0xf;
+  read1->rw = 0;
+  read1->byteen = 0xffff;
+  read1->addr = addr1;
+  read1->data = data; 
+  read1->tag = 0xff;
+
+  //read req
+  core_req_t* read2 = new core_req_t;
+  read2->valid = 0xf;
+  read2->rw = 0;
+  read2->byteen = 0xffff;
+  read2->addr = addr2;
+  read2->data = data; 
+  read2->tag = 0xff;
+
+  //read req
+  core_req_t* read3 = new core_req_t;
+  read3->valid = 0xf;
+  read3->rw = 0;
+  read3->byteen = 0xffff;
+  read3->addr = addr3;
+  read3->data = data; 
+  read3->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  //sim->send_req(write);
+  sim->send_req(read1);
+  sim->send_req(read2);
+  sim->send_req(read3);
+
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+int FLUSH(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  sim->send_req(write);
+  sim->send_req(read);
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+
+int BACK_PRESSURE(CacheSim *sim){
+  unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
+  unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
+  unsigned int rsp[4] = {0,0,0,0};
+  char responded = 0;
+  
+  //write req
+  core_req_t* write = new core_req_t;
+  write->valid = 0xf;
+  write->rw = 0xf;
+  write->byteen = 0xffff;
+  write->addr = addr; 
+  write->data = data;
+  write->tag = 0xff;
+
+  //read req
+  core_req_t* read = new core_req_t;
+  read->valid = 0xf;
+  read->rw = 0;
+  read->byteen = 0xffff;
+  read->addr = addr;
+  read->data = addr; 
+  read->tag = 0xff;
+  
+  // reset the device
+  sim->reset();
+
+  //queue reqs
+  for (int i = 0; i < 10; i++){
+    sim->send_req(write);
+  }
+  sim->send_req(read); 
+
+  sim->run();
+
+  bool check = sim->assert_equal(data, write->tag);
+  
+  return check;
+}
+
+
+int main(int argc, char **argv)
+{
+  //init
+  RAM ram;
+	CacheSim cachesim;
+  cachesim.attach_ram(&ram);
+  int check = REQ_RSP(&cachesim);
   if(check){
     std::cout << "PASSED" << std::endl;
   } else {
     std::cout << "FAILED" << std::endl;
   }
   
+
+
 	return 0;
 }