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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 03:38:00 -04:00
parent 460aabf6b1
commit 9b476f1e17
97 changed files with 3127 additions and 18563 deletions
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25
hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
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@@ -1,33 +1,20 @@
`ifndef VX_GPU_DRAM_DCACHE_REQ
`define VX_GPU_DRAM_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_req_inter
#(
parameter BANK_LINE_WORDS = 2
)
();
interface VX_gpu_dcache_dram_req_inter #(
parameter BANK_LINE_WORDS = 2
) ();
// DRAM Request
wire dram_req;
wire dram_req_write;
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [31:0] dram_req_size;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire dram_req_full;
// Snoop
wire dram_because_of_snp;
wire dram_snp_full;
// DRAM Cache can't accept response
wire dram_fill_accept;
// DRAM Cache can't accept request
wire dram_req_delay;
wire dram_rsp_ready;
endinterface