RTL code refactoring

hw/rtl/VX_generic_register.v

@@ -1,24 +1,24 @@
+module VX_generic_register #( 
+	parameter N, 
+	parameter PassThru = 0
+) (
+/* verilator lint_off UNUSED */
+	input wire          clk,
+	input wire          reset,
+	input wire          stall,
+	input wire          flush,
+/* verilator lint_on UNUSED */
+	input wire[N-1:0]  	in,
+	output wire[N-1:0] 	out
+);
 
-module VX_generic_register 
-	#( parameter N = 1, parameter Valid = 1)
-	(
-		input wire           clk,
-		input wire           reset,
-		input wire           stall,
-		input wire           flush,
-		input wire[(N-1):0]  in,
-		output wire[(N-1):0] out
-	);
-
-	if (Valid == 0) begin
-
+	if (PassThru) begin
 		assign out = in;
-
 	end else begin
 
-		reg[(N-1):0] value;
+		reg [(N-1):0] value;
 
-		always @(posedge clk or posedge reset) begin
+		always @(posedge clk) begin
 			if (reset) begin
 				value <= 0;
 			end else if (flush) begin
@@ -29,7 +29,6 @@ module VX_generic_register
 		end
 
 		assign out = value;
-
 	end
 
 endmodule