minor fixes
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@@ -1,7 +1,7 @@
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vortex_afu.json
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+define+NDEBUG
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+define+SCOPE
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#+define+SCOPE
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#+define+DBG_PRINT_CORE_ICACHE
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#+define+DBG_PRINT_CORE_DCACHE
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@@ -204,7 +204,7 @@ begin
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end
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MMIO_CSR_SCOPE_CMD: begin
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`ifdef DBG_PRINT_OPAE
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$display("%t: CSR_SCOPE_CMD: %0d", $time, 64'(cp2af_sRxPort.c0.data));
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$display("%t: CSR_SCOPE_CMD: %0h", $time, 64'(cp2af_sRxPort.c0.data));
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`endif
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end
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default: begin
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@@ -246,7 +246,7 @@ begin
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MMIO_CSR_SCOPE_DATA: begin
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mmio_tx.data <= csr_scope_data;
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`ifdef DBG_PRINT_OPAE
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$display("%t: SCOPE: data=%0d", $time, csr_scope_data);
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$display("%t: SCOPE: data=%0h", $time, csr_scope_data);
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`endif
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end
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default: mmio_tx.data <= 64'h0;
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@@ -815,9 +815,9 @@ end
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`SCOPE_ASSIGN(scope_snp_rsp_tag, vx_snp_rsp_tag);
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`SCOPE_ASSIGN(scope_snp_rsp_ready, vx_snp_rsp_ready);
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`STATIC_ASSERT($bits({`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST}) == 490, "oops!")
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`STATIC_ASSERT($bits({`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST}) == 491, "oops!")
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wire force_changed = (scope_icache_req_valid && scope_icache_req_ready)
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wire scope_changed = (scope_icache_req_valid && scope_icache_req_ready)
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|| (scope_icache_rsp_valid && scope_icache_rsp_ready)
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|| ((| scope_dcache_req_valid) && scope_dcache_req_ready)
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|| ((| scope_dcache_rsp_valid) && scope_dcache_rsp_ready)
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@@ -826,6 +826,9 @@ wire force_changed = (scope_icache_req_valid && scope_icache_req_ready)
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|| (scope_snp_req_valid && scope_snp_req_ready)
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|| (scope_snp_rsp_valid && scope_snp_rsp_ready);
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wire scope_start = vx_reset;
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wire scope_stop = 0;
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VX_scope #(
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.DATAW ($bits({`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST})),
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.BUSW (64),
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@@ -834,9 +837,9 @@ VX_scope #(
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) scope (
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.clk (clk),
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.reset (SoftReset),
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.start (vx_reset),
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.stop (0),
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.changed (force_changed),
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.start (scope_start),
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.stop (scope_stop),
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.changed (scope_changed),
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.data_in ({`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST}),
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.bus_in (csr_scope_cmd),
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.bus_out (csr_scope_data),
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