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RAM blocks inference fixes

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This commit is contained in:
Blaise Tine
2020-11-30 14:02:47 -08:00
parent 5758ef9ebf
commit 97739e9dcf
27 changed files with 218 additions and 189 deletions
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134
hw/rtl/libs/VX_dp_ram.v
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@@ -21,33 +21,40 @@ module VX_dp_ram #(
output wire [DATAW-1:0] dout
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
localparam DATA32W = DATAW / 32;
localparam BYTEEN32W = BYTEENW / 4;
if (FASTRAM) begin
if (BUFFERED) begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (BUFFERED) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
if (rden)
dout_r <= mem[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
end
end
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
assign dout = dout_r;
@@ -55,48 +62,58 @@ module VX_dp_ram #(
`UNUSED_VAR (rden)
if (RWCHECK) begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
if (RWCHECK) begin
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
assign dout = mem[raddr];
end
assign dout = mem[raddr];
end else begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
assign dout = mem[raddr];
end
end
end
@@ -104,79 +121,88 @@ module VX_dp_ram #(
if (BUFFERED) begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
if (rden)
dout_r <= mem[raddr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
end
end
always @(posedge clk) begin
if (rden)
dout_r <= mem[raddr];
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
assign dout = mem[raddr];
end
assign dout = mem[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i * 8 +: 8] <= din[i * 8 +: 8];
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[waddr] <= din;
end
end
assign dout = mem[raddr];
assign dout = mem[raddr];
end
end
end
end