RAM blocks inference fixes

2020-11-30 14:02:47 -08:00
parent 5758ef9ebf
commit 97739e9dcf
27 changed files with 218 additions and 189 deletions
--- a/hw/rtl/libs/VX_divide.v
+++ b/hw/rtl/libs/VX_divide.v
@@ -73,8 +73,8 @@ module VX_divide #(
        assign quotient  = quotient_unqual [WIDTHQ-1:0];
        assign remainder = remainder_unqual [WIDTHR-1:0];
    end else begin
-        reg [WIDTHN-1:0] quotient_pipe [0:LATENCY-1];
-        reg [WIDTHD-1:0] remainder_pipe [0:LATENCY-1];
+        reg [WIDTHN-1:0] quotient_pipe [LATENCY-1:0];
+        reg [WIDTHD-1:0] remainder_pipe [LATENCY-1:0];

        for (genvar i = 0; i < LATENCY; i++) begin
            always @(posedge clk) begin