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RAM blocks inference fixes

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This commit is contained in:
Blaise Tine
2020-11-30 14:02:47 -08:00
parent 5758ef9ebf
commit 97739e9dcf
27 changed files with 218 additions and 189 deletions
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6
hw/rtl/cache/VX_bank.v vendored
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@@ -498,6 +498,7 @@ if (DRAM_ENABLE) begin
end else begin
`UNUSED_VAR (mshr_pending_hazard_unqual_st0)
`UNUSED_VAR (addr_st0)
assign {tag_st1, mem_rw_st1, mem_byteen_st1, tid_st1} = inst_meta_st1;
@@ -510,7 +511,7 @@ end else begin
assign writedata_st1= writedata_st0;
assign inst_meta_st1= inst_meta_st0;
assign snp_inv_st1 = snp_inv_st0;
assign addr_st1 = addr_st0;
assign addr_st1 = reqq_addr_st0[`LINE_SELECT_ADDR_RNG];
assign dirty_st1 = 0;
assign readtag_st1 = 0;
assign miss_st1 = 0;
@@ -782,7 +783,8 @@ end
VX_generic_queue #(
.DATAW(`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE(CWBQ_SIZE)
.SIZE(CWBQ_SIZE),
.BUFFERED(1)
) cwb_queue (
.clk (clk),
.reset (reset),

40
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -29,18 +29,6 @@ module VX_cache_core_rsp_merge #(
input wire core_rsp_ready
);
if (NUM_REQUESTS > 1) begin
wire [`BANK_BITS-1:0] sel_idx;
VX_rr_arbiter #(
.N(NUM_BANKS)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (per_bank_core_rsp_valid),
`UNUSED_PIN (grant_valid),
.grant_index (sel_idx),
`UNUSED_PIN (grant_onehot)
);
reg [NUM_REQUESTS-1:0] core_rsp_valid_unqual;
reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual;
@@ -48,6 +36,19 @@ module VX_cache_core_rsp_merge #(
reg [NUM_BANKS-1:0] core_rsp_bank_select;
if (CORE_TAG_ID_BITS != 0) begin
wire [`BANK_BITS-1:0] sel_idx;
VX_rr_arbiter #(
.N(NUM_BANKS)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (per_bank_core_rsp_valid),
`UNUSED_PIN (grant_valid),
.grant_index (sel_idx),
`UNUSED_PIN (grant_onehot)
);
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = per_bank_core_rsp_tag[sel_idx];
@@ -65,17 +66,10 @@ module VX_cache_core_rsp_merge #(
end
end else begin
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_valid_unqual[per_bank_core_rsp_tid[sel_idx]] = per_bank_core_rsp_valid[sel_idx];
core_rsp_tag_unqual = 'x;
core_rsp_tag_unqual[per_bank_core_rsp_tid[sel_idx]] = per_bank_core_rsp_tag[sel_idx];
core_rsp_data_unqual = 'x;
core_rsp_data_unqual[per_bank_core_rsp_tid[sel_idx]] = per_bank_core_rsp_data[sel_idx];
core_rsp_bank_select = 0;
core_rsp_bank_select[sel_idx] = 1;
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = 'x;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]

4
hw/rtl/cache/VX_data_store.v vendored
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@@ -43,9 +43,9 @@ module VX_data_store #(
end
VX_dp_ram #(
.DATAW(`BANK_LINE_WORDS * WORD_SIZE * 8),
.DATAW(BANK_LINE_SIZE * 8),
.SIZE(`BANK_LINE_COUNT),
.BYTEENW(`BANK_LINE_WORDS * WORD_SIZE),
.BYTEENW(BANK_LINE_SIZE),
.BUFFERED(0),
.RWCHECK(1)
) data (

2
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -64,7 +64,7 @@ module VX_snp_forwarder #(
VX_cam_buffer #(
.DATAW (SRC_ADDR_WIDTH + 1 + SNP_TAG_WIDTH),
.SIZE (SNRQ_SIZE)
) snp_fwd_cam (
) req_metadata_buf (
.clk (clk),
.reset (reset),
.write_addr (sfq_write_addr),