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fpga build refactoring

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This commit is contained in:
Blaise Tine
2021-04-29 06:17:28 -07:00
parent 2216a3059d
commit 95f057bc2e
16 changed files with 185 additions and 208 deletions
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2
hw/rtl/VX_define.vh
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@@ -243,7 +243,7 @@
`define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0)
// Block size in bytes
`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
// Word size in bytes
`define IWORD_SIZE 4

4
hw/rtl/afu/vortex_afu.sv
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@@ -10,9 +10,7 @@
/* verilator lint_off IMPORTSTAR */
import ccip_if_pkg::*;
import local_mem_cfg_pkg::*;
/* verilator lint_on IMPORTSTAR */
`define MEM_BLOCK_SIZE LOCAL_MEM_DATA_N_BYTES
/* verilator lint_on IMPORTSTAR */
`include "VX_define.vh"